K82: reset reason "Stop Mode Acknowledge Error Reset"

[EugeneHiihtaja]

Hello !

I'm using LLS3 low power mode and sometimes I'm not able to go in it and sudden reset happens.

I have decode reset reason and it is always "Stop Mode Acknowledge Error Reset".

External LLWU pins are configured for wakeup and LPTIMER0 as well.

As usually  this type of reset is happens 2-3 times when I  flash K82 by JTAG.

It looks like some preconditions are not met and I need to clean someting after cold start/reboot.

Is any idea how-to  check all LLS3 preconditions and clean  pending events what might have effect to entering to LLS3 ?

MCUExpresso IDE and SDK is latest.

Regards,

Eugene

[jingpan]

Hi Eugene,

SACKERR error reset is generated if the core attempts to enter stop mode, but not all modules acknowledge stop mode within 1025 cycles of the 1 kHz LPO clock. Please check following conditions:

1. DSPI slave transfer ongoing, saying DSPI_PCS active, but transfer not ended in 1024 LPO cycles.

2. IIC transfer ongoing, not sure how to duplicate that case on silicon, but IIC can generate the SACKERR error reset

3. PMC HRUN mode, can not enter STOP mode, SACKERR reset will happen if trying enter STOP mode from HRUN mode

4. DMA transfer ongoing.

5. USB transfer ongoing,

6. LPUART transfer ongoing.

7. GPIO event

Regards,

Jing

[EugeneHiihtaja]

Hi Jing !

1.

I'm not using DSPI,USB, DMA for sure. Even all DMAs disabled by AIPS. MCU in RUN mode when enter to routine what prepare MCU for LLS3 mode.

2.

LPUART1 is used for traces and interrupt driven input ( terminal ).

Output is always flushed :

while (
!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *) DEBUG_UART)))
{
}

3. I2C slave is active but no transmission for sure. I2C master is active ( poll sensor periodically) but no transaction becouse MCU in other task

   what used for execute LLS3 entry routine.

4. A lot of external GPIOs are active in interrupt  mode and when I enter to LLS3 mode I have enabled all of them as LLWU wakeup sources.

6. 

LPTIMER is also used as source ( and regular interrupts as well ) of wakeup and timer is always active ( 10 s wakeup loop for testing ).

Moment for entry can much with end of timer

6.

Have it sense to disable peripheral interrupts and GPIO interrupts before LLS3 and enable those when resume back ?

7.

Have it sense to clean LLWU by LLWU_ClearExternalWakeupPinFlag and GPIO events by PORT_ClearPinsInterruptFlags() ?

8.

How freely I can manipulate with LLWU_IRQ ?

I enable it when all sources is configured

/* All wake up sources are configured. */
EnableIRQ(LLWU_IRQn);

// Enter to LLS3

power_user_config_t targetConfig;
targetConfig.enableLpoClock = true;
targetConfig.mode = kAPP_PowerModeLls;
PM_PowerModeSwitch(&targetConfig, NULL);

....

//Resumed

DisableIRQ(LLWU_IRQn);  // Disable

9. Can MPU have some effect ?

10. List if reasons look dangerous.

Does it possible to disable this type of reset and have routine what put MCU again to LLS3 if first trial are not succesfull ?

Regards,

Eugene

[EugeneHiihtaja]

Hi Jing !

I can see that issue happens much more rare if I haven't use LPTIMER0.

I'm periodically  reinit it by using sequence :

1.

vTaskSuspendAll();

/* Stop timer. */
LPTMR_StopTimer(LPTMR0);
LPTMR_DisableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable);
DisableIRQ(LPTMR0_LPTMR1_IRQn);
LPTMR_ClearStatusFlags(LPTMR0, kLPTMR_TimerCompareFlag);
NVIC_ClearPendingIRQ(LPTMR0_LPTMR1_IRQn);

/* If timeout is specified, init with desired timeout in s. */
if (timeout_s > 1)
{
LPTMR_SetTimerPeriod(LPTMR0, LPO_CLK_FREQ * (timeout_s - 1U));
LPTMR_EnableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable);
NVIC_ClearPendingIRQ(LPTMR0_LPTMR1_IRQn);
EnableIRQ(LPTMR0_LPTMR1_IRQn);
LPTMR_StartTimer(LPTMR0);
}

xTaskResumeAll();

And when I enter to LLS3 mode, LLWU capabilities are enabled :

LLWU_EnableInternalModuleInterruptWakup(LLWU, LLWU_LPTMR_IDX, true);

But even I enable LLWU all the time when I restart timer , it dosn't help.

It means running Lptimer0 have large effect for erase and right sequence is need for enable/reenable it if it used as wakeup source as well.

2. By the way is any effect might have TRNG generator and LTC accelerator ? There are initialized as well ( but  not used at moment when LLS3 is initiated.).

Regards,

Eugene

[EugeneHiihtaja]

Hi Jing !

Can SACKERR error also be connected to clock stabilisation on oscillators ( System and RTC ) and IRC48 and  LPO ?

In my system WDOG, RTC and LPO ( for LPTIMER ) are enabled and all clock sources are enabled.

TRNG and LTC is also initialized at startup. After that RTOS starts and clocked from Systick.

If I entry to LLS3 mode first after 3000 ms when RTOS is started -> as usually 1-5  resets can happens.

If after 5000 ms -> I haven't seen any reset yet and testing ongoing.

Is any way to check if all clocks are stable ?

Regards,

Eugene

[jingpan]

Hi Eugene,

In the reference manual page 190, it says that polls stop acknowledge indications from the non-core crossbar masters (DMA), supporting peripherals (SPI, PIT, TRNG) and the Flash Controller for indications that System Clocks, Bus Clock and/or Flash Clock need to be left enabled to complete a previously initiated operation, effectively stalling entry to the targeted low power mode. When all acknowledges are detected, System Clock, Bus Clock and Flash Clock are turned off at the same time.
LPTMR can be used to wake up. You can see that frdm82k_power_mode_switch demo use LPTMR to wake up.
There are some suggestions in https://community.nxp.com/message/309382. Please take a look.

Regards,

Jing

[EugeneHiihtaja]

Hi Jing !

I have PIT timer running as well but looks like deinit TRNG before LLS3 and reenable it after help with reboot problem with my set of HW.

I can entry to LLS3 as fast as need.

Is this case with TRNG is documented in errata somewhere ?

It should be explanation why reset is not happens after 5S of cold reboot but easily happens after 3s.

Does internal stabilizadion/post/full initialization  of TRNG take so long time ?

And if I disable/enable TRNG so often what kind of effect it have for quality of random values ?

Regards,

Eugene

[jingpan]

Hi Eugene,

I can't see any record about TRNG in errata. I don't think disable/enable TRNG so often what kind of effect it have for quality of random values. But I see you have prompt submit a question about TRNG last year. K82 SDK example for TRNG 

So could the long time caused by the TRNG clock setting?

Before transitioning TRNG0 to low power mode, does software check that MCTL[TSTOP_OK] is a 1?

Regards,

Jing

[EugeneHiihtaja]

Hi Jing !

You mean this code in SMC_SetPowerModeLls :

/* check whether the power mode enter LLS mode succeed */
if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
{
return kStatus_SMC_StopAbort;
}
else
{
return kStatus_Success;
}

If I not disable TRNG and try to go LLS3 faster than 5s after reboot. MCU reboot and decoding reboot reason show SMAER.

TRNG initialized at early boot time and initialisation is OK.

It would be nice if attempt to go  to LLS3 mode just return error but it always cause reboot what is noncontrolled behaviour and looks very dangerous.

How to get of this type of reset and just make second trial of LLS3 after some timeout.

br, Eugene

[jingpan]

Hi,

No, I mean bit 13 in TRNG0 Miscellaneous Control register (TRNG0_MCTL). It says software should check that this bit is a 1 before transitioning TRNG0 to low power mode (TRNG0 clock stopped).

Regards,

Jing