K70 and DDR2 SDRAM unstable work

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K70 and DDR2 SDRAM unstable work

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Contributor III

Hi All,
on our custom board ( based on MK70FX512VMJ15 and MT47H64M16HR-3 AAT:H TR) we have problems that appear randomly in the field. The device can work up to 20 days without any problems. Then one DDR byte lane can stop working correctly. Thus, it is very similar to "e10521 of Errata KINETIS_K_4N96B".
And we can read all EVEN addresses as 0x00 with byte access. All ODD addresses are still correct.
We have already read a 32-bit value from address 0x400A_E188. This is the current RCR delay value. And it is always like 0x14,0x13,0x12. And it does not change if the K70 DDR controller enters into that abnormal mode. To restore the normal work of the device we just re-initialize the DDR controller. And everything starts to work.
We could see the problem on some devices only. Other devices do not have that issue at all.

We tried to heat the device up to 100°С. And we can't enter the device into that mode in the lab. 

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Contributor II

Hi Vitaliy

We are experiencing a similar or possibly the same issue that occurs at cold temperatures (near -40C).

Did you end up finding a solution to your problem?

Regards,

Jon

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Contributor I

Hi We also found the same problem, SIM_MCR & = ~ 0 XFF.After (near 80C) to normal, But (near -10C)  appear the same problem, do you have any solution?

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Contributor III

Hi, 

perhaps you could read this article (K70 DDR2 read failure with increasing temperature ) and see if the proposed solution is also applicable to your case.

Best regards.

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NXP TechSupport
NXP TechSupport

Dear Vitaliy Avramenko,  have you tried the workaround of the  errata? I think the workaround does not fix the problem it only lower the probability of happening, this problem should be fixed in the Next Mask-set 5N96B.

Best regards

Jonathan

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Contributor III

Hello Jonathan,
yes, we have already  tried the walk around  for that specific problem in the errata.
Few days ago we experimented  with  a 32-bit RCR delay value.
We have  read a 32-bit value from address 0x400A_E188.
And it is always like 0x14,0x13,0x12. And it does not change if the K70 DDR controller enters into that abnormal mode.
Anyway we tried to write the fixed value (0x13)  to 0x400A_E18C and set bit 15 of the 32-bit register at address 0x400A_E184 while the DDR controller fails.
It does not help. The memory does not work.
To restore the normal work of the device we just re-initialize the DDR controller. And everything starts to work.

There is our code we use to initialize/re-initialize the DDR controller

/* Enable DDR controller clock */
    SIM_SCGC3 |= SIM_SCGC3_DDR_MASK;

    /* Enable DDR pads and set slew rate */
    SIM_MCR &= ~0xFF;
    SIM_MCR |= 0xC4;   // bits were left out of the manual so there isn't a macro right now

    DDR_RCR |= DDR_RCR_RST_MASK;

    * (vuint32 *)(0x400Ae1ac) = 0x01030203;

    DDR_CR00 = 0x00000400;
    DDR_CR02 = 0x02000031;
    DDR_CR03 = 0x02020506;
    DDR_CR04 = 0x06090202;
    DDR_CR05 = 0x02020302;
    DDR_CR06 = 0x02904002;
    DDR_CR07 = 0x01000303;
    DDR_CR08 = 0x05030201;
    DDR_CR09 = 0x020000c8;
    DDR_CR10 = 0x03003207;
    DDR_CR11 = 0x01000000;
    DDR_CR12 = 0x04920031;
    DDR_CR13 = 0x00000005;
    DDR_CR14 = 0x00C80002;
    DDR_CR15 = 0x00000032;
    DDR_CR16 = 0x00000001;
    DDR_CR20 = 0x00030300;
    DDR_CR21 = 0x00040232;
    DDR_CR22 = 0x00000000;
    DDR_CR23 = 0x00040302;
    DDR_CR25 = 0x0A010201;
    DDR_CR26 = 0x0101FFFF;
    DDR_CR27 = 0x01010101;
    DDR_CR28 = 0x00000003;
    DDR_CR29 = 0x00000000;
    DDR_CR30 = 0x00000001;
    DDR_CR34 = 0x02020101;
    DDR_CR36 = 0x01010201;
    DDR_CR37 = 0x00000200;
    DDR_CR38 = 0x00200000;
    DDR_CR39 = 0x01010020;
    DDR_CR40 = 0x00002000;
    DDR_CR41 = 0x01010020;
    DDR_CR42 = 0x00002000;
    DDR_CR43 = 0x01010020;
    DDR_CR44 = 0x00000000;
    DDR_CR45 = 0x03030303;
    DDR_CR46 = 0x02006401;
    DDR_CR47 = 0x01020202;
    DDR_CR48 = 0x01010064;
    DDR_CR49 = 0x00020101;
    DDR_CR50 = 0x00000064;
    DDR_CR52 = 0x02000602;
    DDR_CR53 = 0x03c80000;
    DDR_CR54 = 0x03c803c8;
    DDR_CR55 = 0x03c803c8;
    DDR_CR56 = 0x020303c8;
    DDR_CR57 = 0x01010002;

    asm("NOP");

    DDR_CR00 |= 0x00000001;

    while ((DDR_CR30 & 0x400) != 0x400);

    MCM_CR |= MCM_CR_DDRSIZE(1);


Thanks in advance
Vitaliy 

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