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Hi, Chiranjeev,
>>>>>>>As you know both the I2S and I2C signals have to be connected between two boards for a tower system(TWR-K70 and TWR-AUDIO-SGTL), so the buffer circuit such as 74244/74245 is required to enhance the signal driving capability, if both the K70 and SGTL5000 are on the same board, the buffer circuit is unnecessary.
>>>>>> If you use the I2S module of K70 as master(the bit clock I2S_SCLK and frame clock I2S_LRCLK are from K70), the SYS_MCLK clock signal of SGTL5000 must be from I2S module of K70 so that the bit clock/frame clock of I2S module can synchronize with SYS_MCLK. If the I2S module of K70 is slave, the I2S signals(bit clock and frame clock) are driven by SGTL5000, the SYS_MCLK clock signal can be from any source, because the I2S bit clock/frame clock are divider of SYS_MCLK in the case, they are synchronized.
>>>>>Yes, you are right, when you insert SD card, one GPIO pin will be pulled down, which will trigger an interrupt.
BR
XiangJun Rong
Hi, Chiranjeev,
>>>>>>>As you know both the I2S and I2C signals have to be connected between two boards for a tower system(TWR-K70 and TWR-AUDIO-SGTL), so the buffer circuit such as 74244/74245 is required to enhance the signal driving capability, if both the K70 and SGTL5000 are on the same board, the buffer circuit is unnecessary.
>>>>>> If you use the I2S module of K70 as master(the bit clock I2S_SCLK and frame clock I2S_LRCLK are from K70), the SYS_MCLK clock signal of SGTL5000 must be from I2S module of K70 so that the bit clock/frame clock of I2S module can synchronize with SYS_MCLK. If the I2S module of K70 is slave, the I2S signals(bit clock and frame clock) are driven by SGTL5000, the SYS_MCLK clock signal can be from any source, because the I2S bit clock/frame clock are divider of SYS_MCLK in the case, they are synchronized.
>>>>>Yes, you are right, when you insert SD card, one GPIO pin will be pulled down, which will trigger an interrupt.
BR
XiangJun Rong
Hi Xiangjun.rong,
Thank you for your reply!
1) In my design also SGTL5000 and K70 are not in same board.it is connected through a connector
so could you please mention an approx. maximum trace length limit value when we want to have a buffer circuit.
2) Could you please mention maximum trace length for RGB signals to be maintained and when to have a buffer circuit
3)Also mention for Ethernet PHY RMII signals to K70 trace length for clock and signals
Thank you very much
Hi, Chiranjeev,
Regarding the buffer circuit, as you see that the output capability of the digital pins of Kinetis(Digital I/O) is 10mA for High drive strength and 2mA for low drive strength, but the input leakage current for digital pins is less than 20uA typically. so the fan out coefficient is about 2mA/20uA=100, from this perspective, buffer is unnecessary. But I think using buffer can improve the signal quality.
Regarding the maximum trace length, I have not the data, sorry.
Hope it can help you.
BR
Xiangjun Rong