K70 DDR Configuration Issue with TWR-K70

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K70 DDR Configuration Issue with TWR-K70

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ScottKerstein
Contributor III

Hello,


Customer is having a sporadic issue with DDR that i have narrowed down to this line of code:

while (u--) {
*p++ ^= uSeed;
uSeed += 0x01020304;
}
where p is a address in ddr. read/modify/write to ddr, a very bus intensive operation.

The error is always at the block of 4 bytes starting at offset 0x850, (p starts at address 0x848057c8, so address 0x84806018-0x8480601b).

Customer has tried two DDR configs, one based off K70MemCtrol and one that matches the code used by bare metal and MQX.

SIM_MCR &= 0xFFFFFF00; SIM_MCR |= 0x000000c4; DDR_RCR |= DDR_RCR_RST_MASK; DDR_PAD_CTRL = 0x01030203; //micrium (and MQX) DDR_CR00 = 0x00000400; DDR_CR02 = 0x02000031; DDR_CR03 = 0x02020506; DDR_CR04 = 0x06090202; DDR_CR05 = 0x02020302; DDR_CR06 = 0x02904002; DDR_CR07 = 0x01000303; DDR_CR08 = 0x05030201; DDR_CR09 = 0x020000c8; DDR_CR10 = 0x03003207; DDR_CR11 = 0x01000000; DDR_CR12 = 0x04920031; DDR_CR13 = 0x00000005; DDR_CR14 = 0x00C80002; DDR_CR15 = 0x00000032; DDR_CR16 = 0x00000001; DDR_CR20 = 0x00030300; DDR_CR21 = 0x00040232; DDR_CR22 = 0x00000000; DDR_CR23 = 0x00040302; DDR_CR25 = 0x0A010201; DDR_CR26 = 0x0101FFFF; DDR_CR27 = 0x01010101; DDR_CR28 = 0x00000003; DDR_CR29 = 0x00000000; DDR_CR30 = 0x00000001; DDR_CR34 = 0x02020101; DDR_CR36 = 0x01010201; DDR_CR37 = 0x00000200; DDR_CR38 = 0x00200000; DDR_CR39 = 0x01010020; DDR_CR40 = 0x00002000; DDR_CR41 = 0x01010020; DDR_CR42 = 0x00002000; DDR_CR43 = 0x01010020; DDR_CR44 = 0x00000000; DDR_CR45 = 0x03030303; DDR_CR46 = 0x02006401; DDR_CR47 = 0x01020202; DDR_CR48 = 0x01010064; DDR_CR49 = 0x00020101; DDR_CR50 = 0x00000064; DDR_CR52 = 0x02000602; DDR_CR53 = 0x03c80000; DDR_CR54 = 0x03c803c8; DDR_CR55 = 0x03c803c8; DDR_CR56 = 0x020303c8; DDR_CR57 = 0x01010002;

/*
//MemInitTool DDR_CR00 = 0x00000400; // DDRCLS, start DDR_CR02 = 0x02007530; // initaref, tinit DDR_CR03 = 0x02020707; // tccd, wrlat, latgate, latlin DDR_CR04 = 0x07090202; // trasmin, trc, trrd, tbint DDR_CR05 = 0x02020302; // tmrd, trtp, trp, twtr DDR_CR06 = 0x00290402; // intwbr, trasmax, tmod DDR_CR07 = 0x01010303; // ccapen, ap, tckesr, clkpw DDR_CR08 = 0x06030301; // tdal, twr, trasdi, tras DDR_CR09 = 0x020000c8; // bstlen, nocmd, tdll DDR_CR10 = 0x02000808; // trpab, tcpd, tfaw DDR_CR11 = 0x01000000; // trefen, arefmode, aref, regdimm DDR_CR12 = 0x048a001e; // tref, trfc DDR_CR13 = 0x00000005; // pd, trefint DDR_CR14 = 0x00c70002; // txsr, tpdex DDR_CR15 = 0x00000015; // puref, sref, txsnr DDR_CR16 = 0x00000001; // lpctrl, clkdly, qkref DDR_CR17 = 0; DDR_CR18 = 0; DDR_CR19 = 0; DDR_CR20 = 0x00030300; // cksrx, cksre, lpre DDR_CR21 = 0x24040232; // mr1dat0, mr0dat0 DDR_CR22 = 0; DDR_CR25 = 0x0a010201; // aprebit, colsiz, addpins, bnk8 DDR_CR26 = 0x0101ffff; // bnkspt, addcol, cmdage, agecnt DDR_CR27 = 0x00010101; // swpen, rwen, prien, plen DDR_CR28 = 0x00000001; // cmdlatr, bigend, reduc, csmap DDR_CR29=0; DDR_CR30 = 0x00000001; // intack, rsyncrf DDR_CR31 = 0; DDR_CR34 = 0x00000101; // odtwrcs, odtrdcs DDR_CR37 = 0x00000200; // w2wsame, w2rsame, r2wsame, r2rsame DDR_CR38 = 0x00200000; // p0wrcnt, pupcs, pdncs DDR_CR39 = 0x00000020; // wp0, rp0, p0rdcnt DDR_CR40 = 0x00002000; // p1wrcnt, p0typ DDR_CR41 = 0x01010020; // wp1, rp1, p1rdcnt DDR_CR42 = 0x00002000; // p2wrcnt, p1typ DDR_CR43 = 0x02020020; // wp2, rp2, p2rdcnt DDR_CR44 = 0; DDR_CR45 = 0x00070b0f; // p0pri3, p0pri2, p0pri1, p0pri0 DDR_CR46 = 0x0f004000; // p1pri0, p0prirlx, p0ord DDR_CR47 = 0x0100070b; // p1ord, p1pri3, p1pri2, p1pri1 DDR_CR48 = 0x0b0f0040; // p2pri1, p2pri0, p1prirlx DDR_CR49 = 0x00020007; // p2ord, p2pri3, p2pri2 DDR_CR50 = 0x00000040; // p2prirlx DDR_CR51 = 0; DDR_CR52 = 0x02000602; // rddtenbas, phyrdlat, phywrltbs DDR_CR53 = 0; DDR_CR54 = 0; DDR_CR55 = 0; DDR_CR56 = 0x02030000; // wrlatadj, rdlatadj DDR_CR57 = 0x01000000; // odtalten
*/ asm("NOP"); DDR_CR00 |= 0x00000001; while ((DDR_CR30 & 0x400) != 0x400); MCM_CR |= MCM_CR_DDRSIZE(1);

What is the difference in setting DDRCFG in SIM_MCR to half strenght and the other to full strength? Both are design for the same TWR-K70 board.

The bare metal/MQX code version sets DDR_CR53-55 (among other), however this conflicts with the ref manual. It has those as 'RESERVED'. Where did the reserved values come from?

Thank you in advance,
Scott

 

Thread Id: ref:_00D20NBgb._500571g5flJ:ref

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Hui_Ma
NXP TechSupport
NXP TechSupport

Hi Scott,

The K70 SIM_MCR register [DDRCFG] field using to control the DDR memory types and drive strength.

The DDR_CR53-55 register [Reserved] bits field function is not visible to customer.
I do a similar test with TWR-K70F120M board, the 0x84806018 ~ 0x8480601b memory range value was modified during code operation.
For I don't know the customer application, I couldn't check if customer mentioned DDR2 memory range (0x84806018 ~ 0x8480601b) with the incorrect value.
While, if I write the fixed value to those memory range, such as 0x5555AAAA. I will read the correct value from those DDR2 memory range.
I am using below code for K70 Tower board DDR2 controller initialization.
We recommend customer to use the [Kinetis® K70 DDR memory initialization tool(REV 1.11.1)] tool:

void twr_ddr2_script_init(void)
{
    /* Enable DDR controller clock */
    SIM_SCGC3 |= SIM_SCGC3_DDR_MASK;

    /* Enable DDR pads and set slew rate */
    SIM_MCR |= 0xC4;   // bits were left out of the manual so there isn't a macro right now

    DDR_RCR |= DDR_RCR_RST_MASK;

    * (vuint32 *)(0x400Ae1ac) = 0x01030203;

    DDR_CR00 = 0x00000400;    // DDRCLS = 4 is reserved??
    DDR_CR02 = 0x02000031;    
    DDR_CR03 = 0x02020506;
    DDR_CR04 = 0x06090202;
    DDR_CR05 = 0x02020302;
    DDR_CR06 = 0x02904002;
    DDR_CR07 = 0x01000303;
    DDR_CR08 = 0x05030201;
    DDR_CR09 = 0x020000c8;
    DDR_CR10 = 0x03003207;
    DDR_CR11 = 0x01000000;
    DDR_CR12 = 0x04920031;
    DDR_CR13 = 0x00000005;
    DDR_CR14 = 0x00C80002;
    DDR_CR15 = 0x00000032; //  | DDR_CR15_SREF_MASK ;
    DDR_CR16 = 0x00000001;
    DDR_CR20 = 0x00030300;
    DDR_CR21 = 0x00040232;
    DDR_CR22 = 0x00000000;
    DDR_CR23 = 0x00040302;
    DDR_CR25 = 0x0A010201;
    DDR_CR26 = 0x0101FFFF;
    DDR_CR27 = 0x01010101;
    DDR_CR28 = 0x00000003;
    DDR_CR29 = 0x00000000;
    DDR_CR30 = 0x00000001;
    DDR_CR34 = 0x02020101;
    DDR_CR36 = 0x01010201;
    DDR_CR37 = 0x00000200;
    DDR_CR38 = 0x00200000;
    DDR_CR39 = 0x01010020;
    DDR_CR40 = 0x00002000;
    DDR_CR41 = 0x01010020;
    DDR_CR42 = 0x00002000;
    DDR_CR43 = 0x01010020;
    DDR_CR44 = 0x00000000;
    DDR_CR45 = 0x03030303;
    DDR_CR46 = 0x02006401;
    DDR_CR47 = 0x01020202;
    DDR_CR48 = 0x01010064;
    DDR_CR49 = 0x00020101;
    DDR_CR50 = 0x00000064;
    DDR_CR52 = 0x02000602;
    DDR_CR53 = 0x03c80000;
    DDR_CR54 = 0x03c803c8;
    DDR_CR55 = 0x03c803c8;
    DDR_CR56 = 0x020303c8;
    DDR_CR57 = 0x01010002;

    asm("NOP");

    DDR_CR00 |= 0x00000001;

    while ((DDR_CR30 & 0x400) != 0x400);

    MCM_CR |= MCM_CR_DDRSIZE(1);      
}


Have a great day,
Mike

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