K64F maxclock input source for ADC16 and ADHSC

[ffonck]

I've been trying to achieve max clock input for the ADC16 in a MK64FX512Vxx12. According to datasheet K64F Sub-Family Data Sheet this value shouldn't be higher than 18Mhz and ADHSC (High speed conversion) must be set for high frequency clocks:

But, https://www.nxp.com/pages/adc-calculator:ADC_CALCULATOR on the "instructions" section says:

So, can I clear ADHSC to maximize sample rate in spite of performance, or is it mandatory to used ADHSC at maximum clock frequency?

If it is mandatory, above what frequency does ADHSC need to be set?

[jingpan]

Hi ffonck,

Yes, if you don't care about convert accuracy, you can set this bit to zero. The additional 2 clock is used by ADC internal comparator circuit for auto-zero. It allow enough settling time when the ADC clock is fast. Without this 2 clock, previous ADC sampling channel may interfere current channel.

Regards,

Jing