K64: SPI Rx FIFO not available in DMA mode?

[dougprice]

I'm stress testing an Ethernet to Serial converter, mostly it works well, but when receiving larger Ethernet frames (bursts of frames) while also receiving SPI Rx data (that are being unloaded via DMA) I am getting SPI Overrun errors occasionally.

Ethernet is 100 mbps, SPI Rx is 2 mbps. As Ethernet frame size is reduced the SPI overrun problem reduces. With a very much slower SPI (300 kbps) speed there is no problem at any Ethernet Frame size.

My presumption is the MAC transfer into RAM is consuming too much bandwidth and I'm running almost flat out now.

So my latest test was to play with the SPI Rx FIFO disable setting - to my surprise it did not impact the overrun errors either way.

I'm looking for confirmation that in DMA mode the SPI does not use its FIFO.  

(I need to convince the hardware folks to change the module to not use the SPI.)

Much appreciated.

Doug

[jorge_a_vazquez]

Hi Doug Price

According to the Reference Manual for K64F, there isn't anything that could indicate that Rx FIFO is not available when using DMA. Actually the RFDF_DIRS bit in the RSER selects whether a DMA request or an interrupt request is generated.

Are you using SDK drivers in your project? Also, please verify that you are not setting DIS_RXF in SPIx_MCR register, this bit disable receive FIFO, and the receive part of the module operates as a simplified double-buffered SPI.

Best Regards

Jorge Alcala

[dougprice]

Hi Jorge Alcala

My code is based on Processor Expert drivers. DIS_RXF has no effect either way, although TX operations are impacted by its FIFO disable bit.

However, I did confirm my suspicion.  I cascaded a second DMA (onto the one doing the SPI offloading) to toggle a diagnostic pin using the very cool port toggle register so I was able to monitor my incoming data pattern and see when the SPI was being unloaded. I set a break point and began testing.

Sure enough an SPI Overrun interrupt triggered, there was a nasty gap just over 9 bytes long at which time only 2 transfers occurred in quick succession (I'm guessing the data register and the shift register) but if the FIFO was connected I'd have gotten 4 or 5 transfers.

Something of an undocumented feature I'd say.

But thanks for your comments.

Doug