K60FX150M Flexbus

[stanleyfan]

I use the parallel slave device with the K60FX150M,the slave device(ENC624J600) is 16K * 16bit memory. 

 Flexbus used in the 16bit Mux-Mode.

My code is 

#define Cs0BaseAddress (*(uint16 *)(0x60000000))

void Flexbus_init()
{
SIM_SOPT2 |= SIM_SOPT2_FBSL(3);
SIM_SCGC7 |= SIM_SCGC7_FLEXBUS_MASK; //Clock Gate enable
//Pin Mux
PORTD_PCR6 = PORT_PCR_MUX(5); // fb_AD0
PORTD_PCR5 = PORT_PCR_MUX(5); // fb_AD1
PORTD_PCR4 = PORT_PCR_MUX(5); // fb_AD2
PORTD_PCR3 = PORT_PCR_MUX(5); // fb_AD3
PORTD_PCR2 = PORT_PCR_MUX(5); // fb_AD4
PORTC_PCR10 = PORT_PCR_MUX(5); // fb_AD5
PORTC_PCR9 = PORT_PCR_MUX(5); // fb_AD6
PORTC_PCR8 = PORT_PCR_MUX(5); // fb_AD7
PORTC_PCR7 = PORT_PCR_MUX(5); // fb_AD8
PORTC_PCR6 = PORT_PCR_MUX(5); // fb_AD9
PORTC_PCR5 = PORT_PCR_MUX(5); // fb_AD10
PORTC_PCR4 = PORT_PCR_MUX(5); // fb_AD11
PORTC_PCR2 = PORT_PCR_MUX(5); // fb_AD12
PORTC_PCR1 = PORT_PCR_MUX(5); // fb_AD13
PORTC_PCR0 = PORT_PCR_MUX(5); // fb_AD14
PORTB_PCR18 = PORT_PCR_MUX(5); // fb_AD15

PORTD_PCR1 = PORT_PCR_MUX(5); // fb_CS0
PORTD_PCR0 = PORT_PCR_MUX(5); // fb_ALE
PORTC_PCR11 = PORT_PCR_MUX(5); // fb_RW

PORTC_PCR18 = PORT_PCR_MUX(5); // fb_BE15-8
PORTC_PCR19 = PORT_PCR_MUX(5); // fb_BE7-0

FB_CSAR0 =(uint32)&Cs0BaseAddress; //Set Base address

FB_CSCR0 = FB_CSCR_BLS_MASK // set byte lane shift
| FB_CSCR_PS(2) // 16-bit port
| FB_CSCR_ASET(0x1) // assert chip select on second clock edge after address is asserted
| FB_CSCR_AA_MASK
| FB_CSCR_RDAH(1)
| FB_CSCR_WRAH(1)
| FB_CSCR_BEM_MASK
| FB_CSCR_WS(0x2) ; // 2 wait state

FB_CSMR0 = FB_CSMR_BAM(0x0) //Set base address mask for 64K address space
| FB_CSMR_V_MASK; //enable cs

FB_CSPMCR = FB_CSPMCR_GROUP5(2)| FB_CSPMCR_GROUP4(2);

}

And the hardware connections is :

K60                                                   Slave

AD[0:15]            ------>                    AD[0:15]

ALE                    ------>                   ALE

CS0                    ------>                   CS

R/W                    ------->                  R/W

FB_BE15-8        ------->                  B1SEL

FB_BE7-0          ------->                  B0SEL

CS0 ,FB_BE15-8 ,FB_BE7-0   use the Inverter (74HC04M) connect to CS ,B1SEL,B0SEL.

But ,this setup can not be write or read???  what's the problem???

[xiangjun_rong]

Hi, Stanley,

From my perspective, I think your timing is okay. I have browsed the required timing of ENC624J600, it seems that the RD signal has two high pulse  while the CS is High, you can read FOUR bytes instaed of TWO bytes, is it required?

what is wrong with you now? If you connect a logic analyzer for the control signals anaddress/data, can you see something?

If you have issue using FlexBus, because all the Flexbus pin are multiplexed with GPIO pin, i think  you can use GPIO pins to read/write data.

Hope it can help you

BR

Xiangjun rong

[stanleyfan]

Hi xiangjun:

     Thanks, the r/w signal is one plus.  But the B0SEL may two plus ,but i don't need two plus , i just read two bytes in one cycle.

  do{
Enc624J_WriteReg(SFReg_EUDAST,0x1234);
retry--;
}while((Enc624J_readReg(SFReg_EUDAST)!=0x1234)&&(retry>0));

I write a value to certain address, and read back . the read data is not equal to the write value.

If use the GPIO simulate the timing ,it may difficulty.