K60 MCGOUTCLK gets divided by 4

[age]

Hello!

I have a PK60FN1M0VLQ12 CPU on the TWR-K60F120M board and I'd like to configure it to run at 120 MHz from the onboard 50 MHz oscillator. I have studied documentation on the MCG and come up with the following code:

MCG_C7 &= ~MCG_C7_OSCSEL_MASK;
MCG_C2 = MCG_C2_RANGE(0x02) | MCG_C2_IRCS_MASK;
MCG_C1 = MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x04) | MCG_C1_IRCLKEN_MASK;
MCG_C4 &= ~(MCG_C4_DRST_DRS_MASK | MCG_C4_DMX32_MASK);
MCG_C5 = MCG_C5_PRDIV(0x4);
MCG_C6 = MCG_C6_VDIV(28);
while (!(MCG_S & MCG_S_IREFST_MASK));
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2));
MCG_C6 |= MCG_C6_PLLS_MASK;
while (!(MCG_S & MCG_S_LOCK_MASK));
MCG_C1 = MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x04) | MCG_C1_IRCLKEN_MASK;
while ((MCG_S & 0x0CU) != 0x0CU);
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01);

Please note lines 5 and 6: with these division/multiplication values, I end up with a 110 MHz clock, as I have verified by enabling MCGCLKOUT output on TRACE_CLKOUT pin hooking it up with a scope. So, the end equation for frequency calculation is: ((50 / 5) * (16 + 28)) / 4 = ((50 / 5) * 44) / 4 = 110 MHz;

I can not understand where the /4 division comes from; the most I could find is a division by 2 in PLL0. Could someone please show me what I missed? I'm using this reference manual: http://cache.freescale.com/files/microcontrollers/doc/ref_manual/K60P144M150SF3RM.pdf

[chris_brown]

Hi,

There is only a divide by two in the path for MCGOUTCLK.  You measure a divide by 4 in your Trace clock because there is a second divide by 2 in the path to TRACE_CLKOUT.  Please see chapter 5.7.3 in the K60 reference manual. 

Thanks,

Chris

[age]

I am aware of that, and my scope shows exactly 55 MHz in current configuration, which corresponds to 110 MHz core/system clock.

I could not possibly see 110 MHz on the scope, because that would mean the core running at 220 MHz, which is not supported.

[chris_brown · Accepted solution]

Please check your register settings.  From your code, you have set VDIV0 to a multiply factor of 44.  44 * 10 = 440 MHz which is way out of range to begin with.  I'm surprised your PLL is locking. 

[age]

I have created a Processor Expert project with all thr required settings and indeed my PRDIV/VDIV were wrong; should have done that in the first place. Thank you.

[chris_brown]

NP.  Glad I could help.