In our application, the K60 is an I2C slave on two different I2C buses. We are seeing some odd timing with the setup time of the data signal compared to the rising edge of the clock when both bus are active. Has anyone figured out what the slave baud rate control, bit 4 of I2C Control Register 2 does? We are not sure what the master baud rate refers to in the description, either the I2C Frequency Divider Register or the I2C bus master clock rate. Should bit 4 of I2C Control Register 2 be set or not? It seems that the configuration of the I2C Frequency Divider Register effects the data setup time.
I also have this question. I'm using the MKL04Z32VFK4 Kinetis processor and have the MKL04 configured as a slave on the I2C bus. When the MKL04 Slave Baud Rate Control bit is NOT enabled (bit = 0), clock stretching is visible in the oscilloscope waveform when communicating with an external I2C master device at 56kbps. When the MKL04 Slave Baud Rate Control bit is enabled (bit = 1), clock stretching is no longer visible. I'm assuming that this is due to the slave baud rate now being independent of the master baud rate. What I'm wondering is if I operate with the slave baud rate independent of the master baud rate (bit = 1), do I run the risk of the master and slave becoming "out of sync" at some point during communication?
The Slave baud rate bit can be enabled to provide for clock stretching if master is very fast. To a slave, an example of a "very fast" mode is when the master transfers at 40kbps but the slave can capture the master's data at only 10 kbps. For further information you can read this tutorial I2C Tutorial. If the k60 is a slave changes to Frequency divider register will not affect the baudrate of I2C communication. The baudrate and setup times depend on the Master device which is sending data to K60 Slave.