K60 Flexbus FB_TA signal not terminating bus cycles

[keithgw]

I am talking to an FPGA which is talking to some memory. When I do a read of that memory, the FPGA may need to hold me off longer than 64 waits states, so I must use the FB_TA signal to know when a bus cycle is complete.

It appears that the FB_TA signal doesn’t actually terminate a bus cycle, no matter how I set things up.

I can see on a scope that the FB_TA signal is being generated properly by the FPGA.

I currently have it setup to Auto Acknowledge after 64 waitstates (when I have that off, the bus just hangs).

I see that all bus transactions terminate after the 64 waitstates, not when FB_TA goes low.

Here is my setup code:

   //override pin set up in _bsp_flexbus_setup in MQX

   FB_MemMapPtr fb_ptr = FB_BASE_PTR;
   
    #define ALT5                    0x05
    #define OFF_CHIP_ACCESS_ALLOW   3 
   
    PORT_MemMapPtr  pctl;
    SIM_MemMapPtr   sim = SIM_BASE_PTR;

    fb_ptr->CS[0].CSMR = 0;      //not valid for now, while we are changing

   
    /* Enable clock to FlexBus module */
    sim->SCGC7 |= SIM_SCGC7_FLEXBUS_MASK;
    sim->SOPT2 |= SIM_SOPT2_FBSL(OFF_CHIP_ACCESS_ALLOW);
   
   
    pctl = (PORT_MemMapPtr)PORTB_BASE_PTR;
    pctl->PCR[10] = PORT_PCR_MUX(ALT5); /* FB_AD19 */
    pctl->PCR[11] = PORT_PCR_MUX(ALT5); /* FB_AD18 */
    pctl->PCR[16] = PORT_PCR_MUX(ALT5); /* FB_AD17 */
    pctl->PCR[17] = PORT_PCR_MUX(ALT5); /* FB_AD16 */
    pctl->PCR[18] = PORT_PCR_MUX(ALT5); /* FB_AD15 */
    pctl->PCR[19] = PORT_PCR_MUX(ALT5); /* FB_OE_b */
   
    pctl = (PORT_MemMapPtr)PORTC_BASE_PTR;
    pctl->PCR[0] = PORT_PCR_MUX(ALT5); /* FB_AD14 */
    pctl->PCR[1] = PORT_PCR_MUX(ALT5); /* FB_AD13 */
    pctl->PCR[2] = PORT_PCR_MUX(ALT5); /* FB_AD12 */
    pctl->PCR[3] = PORT_PCR_MUX(ALT5); /* FB_CLKOUT */
    pctl->PCR[4] = PORT_PCR_MUX(ALT5); /* FB_AD11 */
    pctl->PCR[5] = PORT_PCR_MUX(ALT5); /* FB_AD10 */
    pctl->PCR[6] = PORT_PCR_MUX(ALT5); /* FB_AD9 */
    pctl->PCR[7] = PORT_PCR_MUX(ALT5); /* FB_AD8 */
    pctl->PCR[8] = PORT_PCR_MUX(ALT5); /* FB_AD7 */
    pctl->PCR[9] = PORT_PCR_MUX(ALT5); /* FB_AD6 */
    pctl->PCR[10] = PORT_PCR_MUX(ALT5); /* FB_AD5 */
    pctl->PCR[11] = PORT_PCR_MUX(ALT5); /* FB_RW_b */
   
    pctl->PCR[19] = PORT_PCR_MUX(ALT5); /* FB_TA_b */
   
    pctl = (PORT_MemMapPtr)PORTD_BASE_PTR;
    pctl->PCR[0] = PORT_PCR_MUX(ALT5); /* FB_ALE */
    pctl->PCR[1] = PORT_PCR_MUX(ALT5); /* FB_CS0_b */
    pctl->PCR[2] = PORT_PCR_MUX(ALT5); /* FB_AD4 */
    pctl->PCR[3] = PORT_PCR_MUX(ALT5); /* FB_AD3 */
    pctl->PCR[4] = PORT_PCR_MUX(ALT5); /* FB_AD2 */
    pctl->PCR[5] = PORT_PCR_MUX(ALT5); /* FB_AD1 */
    pctl->PCR[6] = PORT_PCR_MUX(ALT5); /* FB_AD0 */
 

    /* Enable FPGA mapped on CS0 */
    fb_ptr->CS[0].CSAR = base_address;
    fb_ptr->CS[0].CSCR = FB_CSCR_EXALE_MASK |      //ALE remains asserted until first pos clock edge after FB_CSn asserts
                         FB_CSCR_WS(64)     |      //Wait states before it auto acknowledges  
                         FB_CSCR_BLS_MASK   |      //Data is right justified on FB_AD
                         FB_CSCR_AA_MASK    |      //Auto Acknowledge -- must be set when no FPGA connnected or will hang forever
                         FB_CSCR_PS(2)      |      //16 bit port size
                         FB_CSCR_BSTR_MASK  |      //allow burst reads
                         FB_CSCR_BSTW_MASK;        //allow burst writes
 
    fb_ptr->CS[0].CSMR = FB_CSMR_BAM(FPGA_CSMR_BAM) | FB_CSMR_V_MASK;      //not write protected
   
    fb_ptr->CSPMCR = 0; //ensure FB_TA is muxed in
 

[RichardR]

I believe you want to change :

    pctl->PCR[19] = PORT_PCR_MUX(ALT5); /* FB_TA_b */

to ALT6 instead of ALT5.

    pctl->PCR[19] = PORT_PCR_MUX(ALT6); /* FB_TA_b */
   
That is the one signal that is different, documentation says due to the fact it is an input to the processor.