K20 120MHz running in "limp mode"? (Slow clock)

[CzechThunder]

Hello all,

Trying to bring up a Kinetis K20 (MK20FN1M0VMD12) and having issues with the clock.

I ported over code from a 120MHz K70 project which should be virtually identical, other than it has DDR and a display controller module.  The code to set the MCG is ported from a K20 120MHz project and comes from Freescale.  It is not using the external oscillator and all the dividers are correct.  Furthermore, changing them has no effect on the apparent execution speed or the TRACE_CLKOUT wave.

I'm not getting close to 120MHz.  The processor seems to run fine using the BMD, but only appears to be running at 20Mhz.  When I bring TRACE_CLKOUT to PORTA6, I see a 5.25MHz square wave, always.  It's as if the processor is in some kind of limp mode.  I've also checked that:

SMC_PMCTRL RUNM mode is 0 (normal run mode)

SIM_CLKDIV1 is set to hex 01240000

{EDIT}

I've also checked PMC_LVDSC1 and that looks normal.  Returns 0x10

Also: Clock source is external 24MHZ crystal oscillator (vs. 50MHz clock on K70 Tower Dev project), NOT using MQX.

Using "bare metal" startup with defines as:

#define CLK0_FREQ_HZ        24000000

#define CLK0_TYPE           CRYSTAL

  #define PLL0_PRDIV      2   

  #define PLL0_VDIV       20

I never see my external crystal oscillator activate.  Is there something else I need to do to turn it on?  PTA18 and PTA19 are not being re-assigned and should be defaulting to the proper outputs.

{/EDIT}

Does this point to anything obvious?

rgds,

Gary

[Jorge_Gonzalez]

Hello Gary Kercheck:

Are you still having this issue?

Mark's suggestion is good. You need to enable the oscillator and configure it to use an external crystal. Those macros you show seem correct but at the end we don't know how those are referenced from the initialization code or if those are used at all.

If you still have problems please let us know or share your project so I can give it a check.

Regards!

Jorge Gonzalez

[mjbcswitzerland]

Gary

You may find that the problem is that your reference code uses an external oscillator and your HW uses a crystal - the configuration is quite different for these two cases. See the following for general MCG overview which may give a bit more practical insight than the user's manual:  µTasker MCG Configuration Support

As reference, the following is the way to configure the K20F120 to generate 120MHz core frequency from 24MHz crystal so that you can compare with what you presently have:

MCG_C2 = (MCG_C2_RANGE_8M_32M | MCG_C2_GAIN_MODE | MCG_C2_EREFS | MCG_C2_LOCRE0); // select crystal oscillator and select a suitable range

MCG_C1 = (MCG_C1_CLKS_EXTERN_CLK | MCG_C1_FRDIV_1024); // switch to external source (the FLL input clock is set to as close to its input range as possible, although this is not absolutely necessary if the FLL will not be used)

while ((MCG_S & MCG_S_OSCINIT) == 0) {} // loop until the crystal source has been selected

while ((MCG_S & MCG_S_IREFST) != 0) {} // loop until the FLL source is no longer the internal reference clock

while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_EXTERN_CLK) {} // loop until the external reference clock source is valid

MCG_C5 = ((CLOCK_DIV - 1) | MCG_C5_PLLSTEN0); // now move from state FEE to state PBE (or FBE) PLL remains enabled in normal stop modes

MCG_C6 = ((CLOCK_MUL - MCG_C6_VDIV0_LOWEST) | MCG_C6_PLLS);

while ((MCG_S & MCG_S_PLLST) == 0) {} // loop until the PLLS clock source becomes valid

while ((MCG_S & MCG_S_LOCK) == 0) {} // loop until PLL locks

SIM_CLKDIV1 = (((SYSTEM_CLOCK_DIVIDE - 1) << 28) | ((BUS_CLOCK_DIVIDE - 1) << 24) | ((FLEX_CLOCK_DIVIDE - 1) << 20) | ((FLASH_CLOCK_DIVIDE - 1) << 16)); // prepare bus clock divides

MCG_C1 = (MCG_C1_CLKS_PLL_FLL | MCG_C1_FRDIV_1024); // finally move from PBE to PEE mode - switch to PLL clock

while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL) {} // loop until the PLL clock is selected

Where

#define CLOCK_DIV 3 // input must be divided to 8MHz..16MHz range (/1 to /8 for 120MHz parts)

#define CLOCK_MUL 30 // the PLL multiplication factor to achieve operating frequency of 120MHz (x16 to x47 possible - divided by 2 at VCO output)

#define SYSTEM_CLOCK_DIVIDE 1 // 120/1 to give 120MHz

#define BUS_CLOCK_DIVIDE 2 // 120/2 to give 60MHz

#define FLEX_CLOCK_DIVIDE 3 // 120/3 to give 40MHz

#define FLASH_CLOCK_DIVIDE 5 // 120/5 to give 24MHz

Noting

MCG_C6_VDIV0_LOWEST is 16 for the K20F120 part in question.

Regards

Mark

Kinetis: µTasker Kinetis support

K20: µTasker Kinetis TWR-K20D72M support  / µTasker Kinetis FRDM-K20D50M support  / µTasker Kinetis TWR-K20D50M support  / µTasker Teensy3.1 support

For the complete "out-of-the-box" Kinetis experience and faster time to market