Is fADCK (ADC conversion clock frequency) referring to the ADC clock source before it is being divided down? I'm assuming its after. But if so, doesn't the "Typical conversion time" example in 23.5.4.6.2 not meet the minimum since 8 MHz/8 = 1 MHz?

[aarond1]

Document Number: KL17P64M48SF6RM

16 bit SE output mode

[EdgarLomeli]

Hello Aaron.

ADCK signal is taken after the clock divider module as shown below:

The complete block diagram is in 23.2.2

I think the example 23.5.4.6.2 it's wrong, the total conversion time it's:

ConversionTime = SFCAdder+AverageNum(BCT+LSTAdder+HSCAdder)

ConversionTime = (3ADCK+5BusK)+32(34ADCK+20ADCK)

ConversionTime = (3/1MHz +5/8MHz)+32(54/1MHz)

ConversionTime =1.731ms

Regards.

[aarond1]

But doesn't 1 MHz not meet the minimum operating condition for a 16 bit mode conversion as you can see from Table 27 in the datasheet?

[EdgarLomeli]

Hi Aaron. 

Unfortunately seems 23.5.4.6.2 example it's only for explanation purpose and does not considerate real operating conditions for the module. If you followed 23.5.4.6.2 configuration, an unexpected behavior would happen. 

Regards.