Interrupt Priority and Preemption on KL05

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Interrupt Priority and Preemption on KL05

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Contributor I

Currently I am writing software for a KL05 microcontroller using Kinetis Design Studio and the Processor Expert Code Generation Tool.  I'm facing an issue in my design with conflicting interrupts. 

 

One interrupt is for servicing a SPI transaction and the other is an either-edge sensitive interrupt on PORTB.  The PORTB interrupt is set to 3 (the lowest level of priority you can go in Cortex-M0) and the SPI interrupt is set to 0 (the highest priority).  I'm using 2 different GPIOs toggled at the beginning and end of each interrupt to know whether or not the interrupt is active.

 

The issue is apparent when looking at the following oscilloscope screenshot:

(Ignoring the light blue signal in this picture, the yellow is the SPI clock line, the pink is the "active" signal of the SPI receive interrupt, and the green is the "active" signal of the PORTB interrupt.)

 

Even though the SPI interrupt is set to the higher priority, there are times (like in the picture) when the PORTB interrupt occurs in the middle of the transaction, that the SPI interrupt is not allowed to interrupt the PORTB interrupt.  It's my understanding that since the SPI interrupt is set to the higher priority, it should be allowed to preempt the PORTB interrupt.  I have done plenty of browsing of the KL05 Reference Manual as well as the ARMv6-M Reference Manual and I can't come to any conclusion.  Am I doing something wrong or is my assumption incorrect?

 

Any help would be appreciated, thanks.

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3 Replies

86 Views
Contributor I

mjbcswitzerland Thanks for the reply.  I discovered the issue being with the Processor Expert code generation tool...

 

The interrupt priority being assigned in the configuration for the tool was not actually being assigned to the interrupt.  The tool put the code in place, but the operation to get a value for the IPR registers always resulted in 0x00000000...  In this way, all of the interrupts I had configured were given a zero priority.

 

Manually writing those registers myself solved the issue.

64 Views
NXP TechSupport
NXP TechSupport

Hi nolankeim,

    Processor Expert is really a little old, even it has the bugs, it is not updated for the kinetis now.

    So, you can refer to the bare-metal code for the KL series.

    https://www.nxp.com/webapp/sps/download/license.jsp?colCode=KL05-SC

 

Best Regards,

Kerry

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104 Views
Specialist V

Hi

As long as you don't have the global interrupt disabled by/in the interrupt routine the higher priority interrupt would always interrupt a lower priority one that is executing.

Regards

Mark
[uTasker project developer for Kinetis and i.MX RT]