Interrupt Latency - Less with 1 or 2 stacks

[JHinkle]

I recently started working with a KL17 which is a M0+ ARM running at 48 MHZ.

I have some concerns about the time it takes to enter and process an interrupt.

The micro has two stacks - main and process.

Currently I was keeping things simple and just using the main stack which means an interrupt will also use it.

My question is, if I engage the process stack -- which ends up being the actual applications stack and the main stack becomes an interrupt stack -- does the time to enter and exit an interrupt decrease with the use of the two stacks because the cpu is just flipping stacks, it does not have to push/pop registers to process the interrupt.

I could not find information in the ARM documentation so I thought I ask here.

Thanks.

Joe

[JHinkle]

Thanks Erich:

I slept on it and and concluded I don't think there is any difference either.  As you stated, it's there when multi-tasking is used to make IRQ processing easier.

Joe

[BlackNight]

Hi Joe,

I have not found any information in the ARM documentation about this. But I think on a Cortex-M0+ the execution time is the same. It could be different (say on an ARM Cortex-M3/M4/M4 if the RAM controller behind the different stacks would have different wait states (different caching and memory controller).

Usinig PSP and MSB makes the most sense with using an operating system where the PSP is used for the threads, and the MSP is used for the interrupt stack, e.g. with FreeRTOS (see https://mcuoneclipse.com/2016/08/28/arm-cortex-m-interrupts-and-freertos-part-3/ ). That way you can keep the thread/task stacks 'free' of interrupt stack items and you don't have to add an adder for the interrupts for each stack, so saving stack memory for each task/thread.

In a bare metal (no multiple tasks, no priviledge mode) I'm using a single stack for the application and the interrupts.

If anyone can find any information about different latency using PSP or MSP, I would be interested too :-).

I hope this helps,

Erich