Input Capture MKM34

[Edrianocarlos]

Hello.

Is that possible to make an input capture in a concatenated timer?

I am able to make a output compare but not a input capture. As i am trying to measure a frequency from 0.2Hz until 9Khz one 32 bits counter would help.

I have already done it using one 16 Bit counter and overflow interrupt. but there always been a chance that both happens at same time make control a little more difficult.

thanks.

[xiangjun_rong]

Hi, Edriano,to speed up to

As Earl Goodrich said, the FLL is unstable from theory, pls use PLL to speed up the external clock from 8MHz to 60mhz. Pls have a try.

BR

Xiangjun Rong

[Edrianocarlos]

Hello Earl, Xiangiun.

Thanks for the answer.

Earl regarding the calibrator it is working well we develop flow meters and have a working product in line that is checked and calibrated with this one.

Regarding the PLL reading the manual the maximum frequency i can achieve is 14.65MHz is thta right? will not be able to reach 60MHz with PLL.

I will keep doing tests and comparatives.

[egoodii]

I see -- the KM34M part does NOT have the 'normal' Kinetis PLL for full CPU operations, only one for 'nominal' 12.288MHz ADC Mclk generation...

Could you supply an external direct 48MHz for the CPU/24MHz Bus?

[Edrianocarlos]

Yes. if the Pll were like in the others Kinets it would be ok.

I am Using the TWR-KM34Z75M kit. i will order an 48MHz Crystal and change it.

It will take some time to buy. when i get this will do another try.

[egoodii]

Just to be clear, it can't be a crystal, as the on-Kinetis oscillator only runs to 32MHz -- needs to be an oscillator.

IF you have a full tower to work with, and an EtherNet I/O board, you can PROBABLY get away with piping-in the 50MHz from that board to the CPU for these test purposes.  TWR-KM34Z75M-SCH.pdf indicates J4 moved to 2/3 will pull a CPU clock from Primary B24.  For at least the TWR-SER that I have, putting a jumper on J3, across 2/3 will route 50MHz to elevator Primary B24.

[xiangjun_rong]

Hi, Edriano,

I think it is okay to use 32 bits counter by using concatenated timers. In order to avoid the counter change during two Timer counter reading, I suggest you set the SCS bits for the concatenated timers to be the same and enable both concatenated timers capture function, in this setting, when the capture event happens, both Timer counters will saved their counters to respective CAPT registers by the capture triggering, but you only enable one Timer to generate interrupt by setting the IEFIE bit, in the ISR, you can read both TMRx_CAPT register and get the tick numbers.

Hope it can help you.

BR

Xiangjun Rong

[Edrianocarlos]

Hello Xiangjun.

thanks for your answer.

that is what i am doing but every time i get an input when i am doing a high frequency meassure lets say 5000Hz the capt1 is correct 4000 for 20MHz clock but tick2 should be 0 instead it is one.

void Inic_Timer(void)
{
  SIM_SCGC5 |= SIM_SCGC5_TMR0_MASK + SIM_SCGC5_TMR1_MASK +SIM_SCGC5_TMR2_MASK  +SIM_SCGC5_TMR3_MASK + SIM_SCGC5_PORTF_MASK;
  PORTF_PCR0 = PORT_PCR_MUX(0x03);
  TMR2_CTRL =   TMR_CTRL_CM(0)     // Cascaded counter mode (up/down)4
  + TMR_CTRL_PCS(8)   // IP bus clock divide by 1 prescaler
  + TMR_CTRL_SCS(2)   // Counter 0 input pin
  + TMR_CTRL_OUTMODE(0); // Asserted while counter is active
    // LENGHT = 0 DIR=0 ONCE=0 COINIT=0
  TMR3_CTRL =    TMR_CTRL_CM(7) // Cascaded counter mode (up/down)4
  + TMR_CTRL_PCS(6)    // ICounter 2 output
  + TMR_CTRL_SCS(2)   // Counter 0 input pin
  + TMR_CTRL_OUTMODE(0); // Asserted while counter is active
    // LENGHT = 0 DIR=0 ONCE=0 COINIT=0
  TMR2_SCTRL = TMR_SCTRL_CAPTURE_MODE(1) + TMR_SCTRL_IEFIE_MASK; //Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input
  TMR3_SCTRL = TMR_SCTRL_CAPTURE_MODE(1); //Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input
  TMR3_CNTR = 0X0000;
  TMR2_CNTR = 0X0000;
  TMR3_CSCTRL = TMR_CSCTRL_DBG_EN(0)+ TMR_CSCTRL_ROC_MASK; //Continue with normal operation during debug mode. (default)
  TMR2_CSCTRL = TMR_CSCTRL_DBG_EN(0)+ TMR_CSCTRL_ROC_MASK; //Continue with normal operation during debug mode. (default)
  valor1 = TMR2_CAPT;
  int_timer = 0;
  TMR2_SCTRL &= ~TMR_SCTRL_IEF_MASK;
  TMR3_SCTRL &= ~TMR_SCTRL_IEF_MASK;
  NVIC_EnableIRQ(TMR2_IRQn);
  NVIC_SetPriority(TMR2_IRQn,0);
  TMR2_CTRL |= TMR_CTRL_CM(1); /* Run counter */
}
void TMR2_IRQ_ISR(void)
{
  valor1 = TMR2_CAPT;
  valor_tot = TMR3_CAPT;
  TMR2_SCTRL &= ~TMR_SCTRL_IEF_MASK;
  TMR3_SCTRL &= ~TMR_SCTRL_IEF_MASK;
  valor_tot <<= 16;
  valor_tot +=valor1;
  if (int_timer == 0)
  {
  int_timer = 1;
  valor_display = valor_tot;
  acumula = 0;
  soma = 0;
  }
  valor1 = 0;
  valor_tot = 0;
}

[Edrianocarlos]

Ok. that seems that TMR_CSCTRL_ROC is not working for TMR3 in my case the most significant counter.

If i force TMR3_CNT =0  inside the interrupt it is counting right.

Now i have another concern.

It seems like that the PLL is not too stable to make he measurement when i am measuring 1HZ i am having an oscillation of +- 300 ticks.

If this errors were always the same positive or negative there would be no problem but it oscillates.

Do yoy think PLL would be more stable as a clock?

[xiangjun_rong]

Hi, Edriano,

Regarding the PLL accuracy,  I do not think the PLL leads to the error for 1Hz tested signal, do you use internal 32KHz IRC or external clock, I suggest you use external clock and use PLL to multiply it, the external clock is more accurate.

BR

XiangJun Rong

[Edrianocarlos]

Hello Xiangjum.

I am using the 8MHz external oscillator.

At 1hz i can measure 1.99987 ~ 1.00012 that would be ok.

But for 5000Hz i am meassuring 3.9975 ~4002 Hz what does not get to my specifications.

i think i will have to change the microcontroller.

[egoodii]

Not sure what kind of accuracy you expect in a single-period measurement.  Measuring 4KHz with an 8MHz reference only leaves 2000 counts to work with -- the natural 'edge conditions' will mean you will ALWAYS vary from 1999 to 2001 (+/-1 count), meaning the best you can HOPE for is a 3998-4002Hz result.  You need to average (or carry-thru) the counts of 'many' successive edges to get better resolution, OR for a 'little better resolution' run the 'highest possible' internal-bus-clock rate (60MHz in 120MHz parts) with the least prescaler to the timer-counter.

[Edrianocarlos]

Ok.

I am working with 8MHz Crystal and using the FLL t0 speed up to 60MHZ dividing for 3 to achieve bus clock and flash 20MHZ.

So i would spect for example at 5KHz a count of 4000 +-1  that would be 3999 ~ 4001 but i am getting 3997 ~4002. with a very precise calibrator.

For 1Hz it is worst becouse i get 20000275 ~19999885 when cont for more time things get worse.

I can achieve +-1 count using another Microcontroller not from freescale but i would really like to use this kinetis due to the AFE 24 Bits.

[egoodii]

Is this 'precise calibrator' putting out a VERY CLEAN zero-to-Vdd square-wave with <20ns risetime 10to90%? I ask because the FTM is just a bunch of counters -- I am looking to see if we can explain the variance with input-cell-hysteresis/passive-filter/digital-filter and synchronizer reactions, OR if we are truly looking at internal FLL or external crystal(?)/oscillator(?) stability.

You should also know that the FLL clock-multiplier is made of simple counters, and is NOT 'smooth' like PLL modes, running from a locked VCO.  I strongly recommend you change to a PLL mode and try again.