I2S bus K70 and TI - tlv320dac3100

[zilinskyf]

Hello Guys,

I am making new schematic with K70 and TI - tlv320dac3100 low power stereo audio DAC.  I need to check I2S bus which there is used. I am not sure if there is all alright. I haven´t made I2S ever.

I attach some pictures from scheme below.

Best regards

Filip

[xiangjun_rong]

Hi, Filip,

I have checked the data sheet of tlv320dac3100, I think your schematics is correct if you use internal clock of K70 as MCLK or set the SAI in slave mode. As you know that the TLV320DAC3100 can be configured as master or slave, in other words, the WCLK/BCLK can be from tlv320dac3100 or SAI module, I do not know if you set which one is master. If you set the SAI of K70 as master, the MCLK/BCLK/WCLK are all from SAI module.

Assume you set the sampling frequency as 48khz, and word width as 32 bits, I2S mode, the MCLK should be 256*48KHz=12.288Mhz. Do you want to use external 12.288MHz clock source and connect it to I2S0_MCLK? If you use external 12.288MHz clock source, you can connect the clock source to I2S0_MCLK and MCLK pin of tlv320dac3100 so that you can generate BCLK/WCLK from the dividing I2S0_MCLK.

If you use K70 internal clock to generate the MCLK from example Bus clock, MCGPLLCLK,system clock, it is okay, you can write the MDR to divide the above clock source to generate the MCLK/WCLK/BCLK.

If you use the SAI as slave, the BCLK/WCLK are from the tlv320dac3100, it is okay.

Because the  tlv320dac3100 is a programmable device, it is flexiable, anyway, pls determine who is the master, where the MCLK signal is from.

Pls refer to section 3.9.9 I2S configuration in UM of K70 to know the clock configuration.

BR

XiangJun Rong