I need to check the RAM in my project.So I have gone through the MKL17Z datasheet and I came to know that SRAM is divided into SRAM_L and SRAM_u. what is the difference between SRAM_L and SRAM_U???

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

I need to check the RAM in my project.So I have gone through the MKL17Z datasheet and I came to know that SRAM is divided into SRAM_L and SRAM_u. what is the difference between SRAM_L and SRAM_U???

962件の閲覧回数
priyankavorugan
Contributor II

Does the number of cycles used by RAM_L and RAM_Ufor data read and write operations are same???

Does this microcontroller has any persistent RAM space(data is not lost even after reset).

Thanks in advance!!!

0 件の賞賛
返信
4 返答(返信)

781件の閲覧回数
priyankavorugan
Contributor II

Hi,

Then what is the purpose of separating the RAM into two parts???

I have another question;

we can store the variables in either ram or rom address using #pragma in the following way.

define region RAM2= mem:[from 0x20000000 size  0x2000FFFE];

place in RAM2 {readwrite section MY_RAM_DATA};

#pargma default_variable_attributes = @ "MY_RAM_DATA"

__no_init int * volatile ram_pointer;

But how can we store the variable at particular address say 0x20000005 of RAM2 ???

0 件の賞賛
返信

781件の閲覧回数
jeremyzhou
NXP Employee
NXP Employee

Hi,

I'd highly recommend you to assign the variables to a 32bit-align absolute address, just in case.

Hope it helps.
Have a great day,
Ping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 件の賞賛
返信

781件の閲覧回数
egoodii
Senior Contributor III

You will find, as in another thread, that a 'single access' (i.e., unaligned 32-bit) that attempts to CROSS the boundary nets a hard-fault:

NOTE

Burst-access cannot occur across the 0x2000_0000 boundary

that separates the two SRAM arrays. The two arrays should be

treated as separate memory ranges for burst accesses.

If 'nothing else' the split of SRAM allows two masters independent, non-interference simultaneous access (one to each) thru the crossbar switch.

The following simultaneous accesses can be made to different logical halves of the

SRAM:

• Core code and core system

• Core code and non-core master

• Core system and non-core master

The 'best' way to force particular elements to particular address is by defining them as a section thru the linker.  You can 'force' an address in your compiler, but then you are 'on your own' to insure no overlap by the linked objects.

NO SRAM contents are 'directly' affected by reset, but NONE survives power-cycle.  Your device MAY have a 32-byte VBAT register file that, as battery-backed, retains thru power-cycle.

0 件の賞賛
返信

781件の閲覧回数
jeremyzhou
NXP Employee
NXP Employee

Hi,

1. Does the number of cycles used by RAM_L and RAM_Ufor data read and write operations are same?

    Yes.

2. Does this microcontroller has any persistent RAM space(data is not lost even after reset).

    The RAM can keep the data after POR.


Have a great day,
Ping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 件の賞賛
返信