I have problem if SIM_CLCKDIV1[OUTDIV1] >= 3 in MK60DN512ZVLL10

[alessiopaolucci]

I try to do a driver for setting clock in MK60DN512ZVLL10.

The base structure is the same that I have done for the kl25z, and for it all well done.

Instead in MK60DN512ZVLL10 if the outdiv1 (Core clok divider) is >= of 3, the program don't work correctly.

Help me, How I can resolve this problem?

Can be a problem of this specific MCU?

Best regard

Alessio Paolucci

[mjbcswitzerland · Accepted solution]

Hi Alessio

When setting the core clock divider make sure that the bus clock and flash clock dividers are also set correctly. It is, for example, illegal to set a faster flash clock than bus speed, etc.

Regards

Mark

[alessiopaolucci]

Thank's!

The problem was that I'didn't know that, if the core clock divider = 3, the bus clock divider have to be only 3 or a multiple of 3.

I do not know if this thing is written on the Ref Manual. I discovered this from Processor Expert.

Have a nice day!

Alessio

[kerryzhou]

Hi Alessio Paolucci,

    Actually, the K60 reference manual already describ the relationship between  bus clock frequence and the core clock frequnce.

Just like the following:

Wish it helps you!

If you still have question, please contact me！

Have a great day,

Jingjing

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