How to use combined FTM instances

frankschuetz · ‎02-22-2016

Hello,

I use the TWR-K65F180M with KSDK 1.3.0 and KDS 3.0.0.

I have developed successfully a software driver that we can capture a run length of a digital signal. There is a FTM counter for counting the run length and there is a set up of 2 eDMA channels to capture the counting values. There are 2 buffers, one for rising edges and one for falling edges. Each buffer is written by a eDMA channel. If the buffer is complete a DMA ISR is occurred and the counting values can be processed further.

So far so good.

Now, there is a new requirement:

If a high phase of this run length signal is greater than a fix specified value then a digital output must be switch on immediately.

The CPU may not be occurred!

My question is now:

How can I implement this feature?

My idea #1:

It is possible to configure the eDMA channel in this way that the FTM2 counter will be reset on each minor loop? So I could configure maximum counter value of FTM2 counter to the fixed value. And if the counter is overflowed then an interrupt will be generated to set a digital output.

My idea #2 (maybe the better way):

A new instance or FTM is set up (i.e. FTM3) to generate the digital output signal. The counter value of this instance must be reset every time by a positive edge of the captured run length signal and specified fix value will be write into a specified FTM3 register. If the counter value is grater than the fix value then the FTM3 set the output to high. I don't know if it is possible in this way.

Do you have a better idea?

If you have a solution, please can you give me an example?

Thanks in advance!

hedihadhri · ‎09-20-2017

Hi Frank,

i hope you found a solution to your problem. I'm curretly to do a task similar to yours where i have to measure time and use eDMA to treat it. Would you mind send me your code of FTM/eDMA? I'm a little bit lost right now and i'd appreciate your help.Thx in advance.

jeremyzhou · ‎02-22-2016

Hi Frank,

I'd highly recommend that you can choose the Dual Edge Capture mode feature to make it.

For instance, you can also make the digital signal to input the FTM2 pin, as the Dual Edge Capture mode is applicable to measure a pulse width, in the FTM2 interrupt function, you can compare the pulse width to the fix value, if the pulse width is the grater than the fix value, reversal the digital output, or keep same.

Hope it helps.
Have a great day,
Ping

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frankschuetz · ‎02-24-2016

Hi Ping,

I think I can not use the DualEdgeCaptrue mode, because on this point to have a pulse width it is to late. it is a maximum pulse width allowed and if the defined value is reached then something must happen.

The existing capture driver (FTM counter and eDMA mechanism to capture the run length signal) works fine and this new requirement can be solved in a completely separate driver. So, another FTM instance can be used for this.

There is a picture (timing diagram) attached that described the mechanism.

The digital input signal is a run length signal. A new FTM instance is set up and counts. The counter may start only on rising edge from the digital IN signal. The counter may set to initial value (0) on falling edge from the digital IN signal. If the FTM counter value is greater than the specified fix value (red line) then the digital output must be set to on! On the coming falling edge of the digital input the digital output is set to off. The digital output should be a FTM channel output that all the whole process is executed by hardware and the CPU is not occurred.

If it is possible in this way, please give me a little example how to setup the FTM instance(s).

Thanks in advance!

jeremyzhou · ‎02-24-2016

Hi Frank,

According to your statement, my scenario is illustrated below.

1. Configure the FTM2 channel 0 and channel 1 work in Input Capture mode, and channel 0 capture on Rising Edge only, channel 1 capture on falling edge only.

2. FTM2_CNTIN is not 0, however the value of the FTM2_CNTIN is equal to 0xFFFF minus the the specified fix value, and the FTM2_MOD=0xFFFF;

3. When the channel 0 detect the rising edge of the input PWM, then trigger interrupt as the CHnF bit is set. And in the interrupt function, it should update the CNT register with its initial value, CNTIN. However when FTM2_CNT=0xFFFF, in another word, the width of pulse is greater than the the specified fix value. The interrupt function will be triggered again as TOF bit is set. In this time, it need to make the digital output to be set to on.

4. FTM2 channel1 is used to detect the falling edge of the input PWM, then trigger the interrupt when falling edge occurs and the digital output will be set to off in interrupt function.

Hope it helps.
Have a great day,
Ping

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frankschuetz · ‎02-25-2016

Hi Ping,
thank you for your suggestion! I will try it.

I have seen a chapter "45.5.11 PWM synchronization" in the K65/66 reference manual. That describe the synchronization mechanism for FTM register values like MOD, CNTIN, a.s.o.

But I don't know how to setup such a FTM configuration. Maybe it is possible to solve this with these synchronization mechanism that the CPU must not be occurred.

Have you a little example for a FTM setup for that (independent from this requirement is also OK).

Example:

FTM channel 0 works as input capture mode. If a e.g. falling edge is captured then the FTM counter starts from beginning (set MOD). This would help me a lot!

Thanks in advance!

jeremyzhou · ‎02-25-2016

Hi Frank,

The PWM synchronization is not applied to your project, for your project, it's simple to write any value to counter register to updates with its initial value,CNTIN.

I've attached a file which includes a variety of FTM functions, please refer to it for details.
Have a great day,
Ping

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frankschuetz · ‎02-25-2016

I mean, the sub chapter "45.5.11.10 FTM counter synchronization" in reference manual as I described above.

In this sub chapter is described when the FTM counter is updated with the CNTIN register value. But I don't understand who trigger the synchronization event (who set the SWSYNC bit)? A input capture channel that is configured with a rising edge? I have tested it and the interrupt is generated but the SWSYNC bit will not be set - it seems so.