How to trigger ADC at the center of high logic of of bottom PWM signal

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How to trigger ADC at the center of high logic of of bottom PWM signal

How to trigger ADC at the center of high logic of of bottom PWM signal

For motor control and swich mode power supply application, it is required that the ADC sampling is synchronized with PWM signal. In general, most Kinetis sub-family provides FTM, PDB and ADC, it provides a mechanism for ADC converter is synchronizedc with PWM signal.

But the KEA family does not have PDB module, instead, the KEA family provides a simple mechanism which enables PWM signal the FTM module generate can synchronize the ADC converter.

The DOC introduces the mechanism, give the register configuration description, code and scope screenshot on how the PWM signal synchronizes the ADC.

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你好,在这个方法上,如何硬件采集多路通道,谢谢!

Hi, Duffy Tang,

The ADC of KEA family supports FIFO mode, for Motor FOC control, you just need sample TWO current channels, the current of third channels can be acquired by computation, so you can set the ADC converter in FIFO mode, and write the TWO current  channels to the ADCH bits, you can add the other ADC channels to the ADCH bits, set the HTRGME bit in the ADC_SC4 reg(Hardware Trigger Multiple Conversion Enable), in this way, when the hardware trigger signal comes, all the ADC channels will be converted. But the drawback is that there is delay for the two current channels, the delay is about 20 ADC clock, assume the ADC clock is 4MHz, the delay will be 5us. You can estimate the current error the delay leads to.

BR

XiangJun Rong

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Last update:
‎09-25-2018 01:56 AM
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