How to communicate two on board SPI's in TWr-k60F120M

pallenna · ‎03-19-2015

Hi to all,

I am new to SPI interface. now i want interface of on board two SPI's for TWR-K60F120 using SPI communication for this what can i do first.i think it is possible right. for this communication i made SPI0 as Master and SPI1 as Slave mode. my theme is, to send one byte data (ex, 0x1) from master of SPI0 to Slave of SPI1 and receive the one byte data(ex 0x2) from Slave of SPI1 to Master Slave of SPI0. and i am sending my code also please check it once if i did any mistakes.

Thanks and Regards,

Padmaja

Original Attachment has been moved to: hello_world.c.zip

Original Attachment has been moved to: isr.h.zip

jeremyzhou · ‎03-20-2015

Hi Padmaja,

Thank you very much for your focus on Freescale Kinetis product. I'm glad to provide service for you.

Definitely, your purpose can be achieved I'd like to share a demo code for you to refer to as below.

Also you can find another example of SPI communication through the link Re: SPI communication b/w two FRDM-K20D50M Boards

void dspi0_master_dspi2_slave_test(void)
{
    s32 i, data= 0x80011234,data1= 0x80011122;
    int error_count = 0;
    for(i=0; i<256 ; i++,data++,data1++ )
    {
        data_to_slave[i] = data;
        data_from_slave[i] = 0xDEADDEAD;       
        data_to_master[i] = data1;
        data_from_master[i] = 0xDEADDEAD;
    }
   
    data_to_slave[255] |= 0x08000000; //Setting EOQ bit
    data_to_slave[255] &= 0x7FFFFFFF;
   
    /* eDMA Configurations */
    SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
    DMA_MUX_CHCONFIG15 = 0x00;
    DMA_MUX_CHCONFIG14 = 0x00;
    DMA_MUX_CHCONFIG13 = 0x00;
    DMA_MUX_CHCONFIG12 = 0x00;
   
    EDMA_ERQL = 0x0000F000;  // Enable DMA request 15,14,13,12
   
    //Build1.3
    DMA_MUX_CHCONFIG15 = 0x95;  // SPI2 TX DMA request source enable
    DMA_MUX_CHCONFIG14 = 0x94;  // SPI2 RX DMA request source enable
    DMA_MUX_CHCONFIG13 = 0x91;  // SPI0 TX DMA request source enable
    DMA_MUX_CHCONFIG12 = 0x90;  // SPI0 RX DMA request source enable
   
    // SPI0 TX
    tcd.saddr = (uint32)data_to_slave;
    tcd.daddr = (uint32)&SPI0_PUSHR;
    tcd.nbytes = 4;
    tcd.tcdAttr = EDMA_TCD_ATTR_SSIZE_32BIT|EDMA_TCD_ATTR_DSIZE_32BIT ;
    tcd.soff =0x04;
    tcd.doff =0x00;
    tcd.loopcount = 256;
    tcd.channelno = 13;
   
    dma_config(CONFIG_BASIC_XFR, &tcd);
    EDMA_TCD_CSR(13) = 0x08; //set DREQ
    // SPI0 RX
    tcd1.saddr = (uint32)&SPI0_POPR;
    tcd1.daddr = (uint32)data_from_slave;
    tcd1.nbytes = 4;
    tcd1.tcdAttr = EDMA_TCD_ATTR_SSIZE_32BIT|EDMA_TCD_ATTR_DSIZE_32BIT ;
    tcd1.soff =0x00;
    tcd1.doff =0x04;
    tcd1.loopcount = 256;
    tcd1.channelno = 12;
   
    dma_config(CONFIG_BASIC_XFR, &tcd1);
   
    // SPI2 TX   
    tcd2.saddr = (uint32)data_to_master;
    tcd2.daddr = (uint32)&SPI2_PUSHR;
    tcd2.nbytes = 4;
    tcd2.tcdAttr = EDMA_TCD_ATTR_SSIZE_32BIT|EDMA_TCD_ATTR_DSIZE_32BIT ;
    tcd2.soff =0x04;
    tcd2.doff =0x00;
    tcd2.loopcount = 256;
    tcd2.channelno = 15;
   
    dma_config(CONFIG_BASIC_XFR, &tcd2);
    EDMA_TCD_CSR(15) = 0x08; //set DREQ
    // SPI2 RX
    tcd3.saddr = (uint32)&SPI2_POPR;
    tcd3.daddr = (uint32)data_from_master;
    tcd3.nbytes = 4;
    tcd3.tcdAttr = EDMA_TCD_ATTR_SSIZE_32BIT|EDMA_TCD_ATTR_DSIZE_32BIT ;
    tcd3.soff =0x00;
    tcd3.doff =0x04;
    tcd3.loopcount = 256;
    tcd3.channelno = 14;
   
    dma_config(CONFIG_BASIC_XFR, &tcd3);
   
   
   
    /* SPI configurations */
    dspi.br    = 0x00;
    dspi.cpha  = 0x00000000;
    dspi.cpol  = 0x00000000;
   
    // SPI0 config..
    SPI0_MCR = 0x80010C01;
    SPI0_CTAR0 = (0x78000000 +dspi.br) | dspi.cpha | dspi.cpol;
    SPI0_RSER = SPI_RSER_TFFF_RE|SPI_RSER_TFFF_DIRS;
    SPI0_RSER |= SPI_RSER_RFDF_RE|SPI_RSER_RFDF_DIRS;
   
    // SPI2 config...
    SPI2_MCR = 0x00010C01;
    SPI2_CTAR0 = 0x78000000 | dspi.cpha | dspi.cpol;
    SPI2_RSER = SPI_RSER_TFFF_RE|SPI_RSER_TFFF_DIRS;
    SPI2_RSER |= SPI_RSER_RFDF_RE|SPI_RSER_RFDF_DIRS;
    //Enable SPI2
    SPI2_MCR = 0x00010000;

    //Enable SPI0
    SPI0_MCR = 0x80010000;

    //Wait for eDMA fill TX FIFO completion
    dma_config(XFR_OVER_WAIT, &tcd2);//SPI1_TX   
    dma_config(XFR_OVER_WAIT, &tcd); //SPI0_TX   
    //Wait for eDMA completion
    dma_config(XFR_OVER_WAIT, &tcd3);//SPI1_RX
    dma_config(XFR_OVER_WAIT, &tcd1);//SPI0_RX
   
    while(SPI_SR_EOQF != (SPI0_SR & SPI_SR_EOQF))
    {}
    SPI2_MCR = 0x00010001;
    SPI0_MCR = 0x80010001;
    printf("eoqf bit is set\n");
    SPI0_SR = SPI0_SR | SPI_SR_TCF  | SPI_SR_EOQF ;
    printf( "SPI0_SR = 0x%08x\r\n",SPI0_SR); 
   

    //Print the datas   
    for(i=0; i<256 ; i++)
    {
        if((s16)data_to_slave[i] != data_from_master[i])
        { 
            printf("i = 0x%08x\r\n",i);
            printf("data_to_slave = 0x%04x\r\n",(s16)data_to_slave[i]);
            printf("data_from_master = 0x%04x\r\n",(s16)data_from_master[i]);
            error_count++;
            printf("Transmit unsuccessful\n");
        }
   
        if((s16)data_to_master[i] != data_from_slave[i])
        {
            printf("i = 0x%08x\r\n",i);
            printf("data_to_master = 0x%04x\r\n",(s16)data_to_master[i]);
            printf("data_from_slave = 0x%04x\r\n",(s16)data_from_slave[i]);
            error_count++;
            printf("Transmit unsuccessful\n");
        }
   
    }
   
}

Wish it helps.
Have a great day,
Ping

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pallenna · ‎04-13-2015

Hi jeremyzhou,

i am new to i2s interface,now i want interface of on board two I2S's for TWR-K60F120 using I2S communication for this what can i do first. i think it is possible right. for this communication i made I2S0 as Master and I2S1 as Slave mode. my theme is, to send one byte data (ex, 0x1) from master of I2S0 to Slave of I2S1 and receive the one byte data(ex 0x2) from Slave of I2S1 to Master Slave of I2S0. so for this please if have code please post here.and i am doing same thing using SPI but it is also not completed so please give me support for this.

Thanks and Regards,

Padmaja

jeremyzhou · ‎04-15-2015

Hi Padmaja,

I'd like to highly recommend you to create a new thread for your new question, as I'm also not very familiar with the I2C communication.

Thank for your understand.
Have a great day,
Ping

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tsi-chung_liew · ‎04-15-2015

Jeremyzhou,

Can you create a new thread for this I2S?

Thanks!

Regards,

TsiChung

pallenna · ‎03-20-2015

Hi jeremyzhou,

Thanks for your reply,already explained my theme. i want test the SPI0 and SPI1 on board modules using SPI communication for TWR-K60F120M using CW10.2. for this communication i made SPI0 as Master and SPI1 as Slave mode. my theme is, to send one byte data (ex, 0x1) from master of SPI0 to Slave of SPI1 and receive the one byte data(ex 0x2) from Slave of SPI1 to Master Slave of SPI0. and i am sending my code also please check it once if i did any mistakes.and i don't want eDMA and also no need processor expert code. so please help me for this interface.and i am waiting for your helpful suggestions as early as possible.

Thanks and Regards,

Padmaja

jeremyzhou · ‎03-20-2015

Hi Padmaja,

I've had a brief look through the code, I think the initialize procedure of SPI and interrupt definition are correct.

However I didn't find the code about transfer the byte in hello_world.c.

Wish it helps.
Have a great day,
Ping

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pallenna · ‎03-20-2015

Hi jeremyzhou,

Thanks for your reply,i had tried only but it is not correct i think,i tried to send data in polling method for master of SPI0 and SPI1 receives the data of master of SPI0 and then sends the data of SPI1 to the SPI0 in interrupt mode.

i think my code follow is wrong but i mentioned above the my requirement of SPI communication of on board of TWR-K60F120M in that SPI0 as master and SPI1 is Slave on single board. so please send me code for my requirement as soon as possible,i hope you early response from you.

Thanks and Regards,

padmaja

jeremyzhou · ‎03-22-2015

Hi Padmaja,

I was wondering if you can share your whole project, then I can run this on TWR-K60F120M board directly.

I'm looking forward to your reply.
Have a great day,
Ping

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pallenna · ‎03-23-2015

Hi jeremyzhou,

i already posted my code to you, and please check it

once where i can did mistakes and if have any code please post.please give me reply as soon as possible.

Thanks and Regards,

Padmaja

jeremyzhou · ‎03-23-2015

Hi Padmaja,

I've modified your original code and it's exhibited as below, please refer to it for details.




/*
* File:        hello_world.c
* Purpose:        Main process
*
*/

#include "common.h"

void SPI0_Master_init(void);
void SPI1_Slave_init(void);
char hal_spi_transfer_one_byte(char v, char end);


void main(void)
{
    char r;
    SIM_SCGC5 |= (  SIM_SCGC5_PORTA_MASK
                        | SIM_SCGC5_PORTB_MASK
                        | SIM_SCGC5_PORTC_MASK
                        | SIM_SCGC5_PORTD_MASK
                        | SIM_SCGC5_PORTE_MASK);
                       
    //UART5_C2 |= UART_C2_RIE_MASK;//for Receiver Full Interrupt for uart5       
    //enable_irq(55);//Enable UART5_RX IRQ
   
    SPI0_Master_init();
    SPI1_Slave_init();
    //Master send 0x01;
        SPI0_MCR&=~SPI_MCR_HALT_MASK;
        SPI1_MCR&=~SPI_MCR_HALT_MASK;
    hal_spi_transfer_one_byte(0x01,1);
   
    enable_irq(27);//Enable SPI1_ISR
        //Waiting for the data from SPI1
    while(!(SPI0_SR & SPI_SR_RFDF_MASK));
    r=(char)SPI0_POPR;
   
             
}

void SPI0_Master_init(void)
{
    SIM_SCGC6 |= SIM_SCGC6_DSPI0_MASK;//CLK enable for SPI_0 Module
   
    PORTC_PCR4 &= ~PORT_PCR_MUX_MASK;//PCS0 Select PRIMARY - A69
    PORTC_PCR4 |= PORT_PCR_MUX(2);
   
    PORTC_PCR5 &= ~PORT_PCR_MUX_MASK;//SCK Select  PRIMARY - A70
    PORTC_PCR5 |= PORT_PCR_MUX(2);
   
    PORTC_PCR6 &= ~PORT_PCR_MUX_MASK;//SOUT Select PRIMARY - A71
    PORTC_PCR6 |= PORT_PCR_MUX(2);
   
    PORTC_PCR7 &= ~PORT_PCR_MUX_MASK;//SIN Select  PRIMARY - A72
    PORTC_PCR7 |= PORT_PCR_MUX(2);
   
    SPI0_MCR |= (SPI_MCR_MSTR_MASK|SPI_MCR_HALT_MASK);
     
    SPI0_MCR &= ~SPI_MCR_MDIS_MASK;//Clear module disable bit for SPI clocks
    SPI0_MCR |= SPI_MCR_DIS_RXF_MASK |
                SPI_MCR_DIS_TXF_MASK |
                SPI_MCR_CLR_RXF_MASK |
                SPI_MCR_CLR_TXF_MASK;
               
  SPI0_MCR |= SPI_MCR_PCSIS(1<<0); 
             
    SPI0_CTAR0 &= ~SPI_CTAR_FMSZ_MASK;
    SPI0_CTAR0 |= SPI_CTAR_FMSZ(0x7)//Frame Size = 7 + 1
                | SPI_CTAR_DBR_MASK // Duty cycle 50/50
                | SPI_CTAR_PBR(0)//BAUD RATE PRESCALER is 2
                | SPI_CTAR_BR(0x0); //SCK BAUD RATE = (F_busck/PBR)*[(1+DBR)/BR]   
  SPI0_SR =  SPI_SR_RFDF_MASK  /
          |  SPI_SR_RFOF_MASK
          |SPI_SR_TFFF_MASK
          |SPI_SR_TFUF_MASK
          |SPI_SR_TCF_MASK
          |SPI_SR_EOQF_MASK;
    //SPI0_MCR &=~ SPI_MCR_HALT_MASK;
}

void SPI1_Slave_init(void)
{
    SIM_SCGC6 |= SIM_SCGC6_DSPI1_MASK;//CLK enable for SPI_1 Module
   
    PORTE_PCR0 &= ~PORT_PCR_MUX_MASK;//PCS0 Select PRIMARY - B22
    PORTE_PCR0 |= PORT_PCR_MUX(2);
   
    PORTE_PCR1 &= ~PORT_PCR_MUX_MASK;//SOUT Select PRIMARY - B11
    PORTE_PCR1 |= PORT_PCR_MUX(2);
   
    PORTE_PCR2 &= ~PORT_PCR_MUX_MASK;//SCK Select  PRIMARY - B7
    PORTE_PCR2 |= PORT_PCR_MUX(2);
   
    PORTE_PCR3 &= ~PORT_PCR_MUX_MASK;//SIN Select  PRIMARY - B10
    PORTE_PCR3 |= PORT_PCR_MUX(2);
   
    SPI1_MCR &=~ SPI_MCR_MSTR_MASK;
    SPI1_MCR |= SPI_MCR_HALT_MASK;
    SPI1_MCR |= SPI_MCR_PCSIS(1<<0);    //The inactive state of PCSx is high. 

    //SPI1_CTAR0 &= ~SPI_CTAR_FMSZ_MASK;         
    SPI1_CTAR0_SLAVE |= SPI_CTAR_FMSZ(0x7);//Frame Size = 7 + 1
    SPI1_CTAR0_SLAVE &=~ SPI_CTAR_SLAVE_CPHA_MASK ; //Data is captured on the leading edge of SCK and changed on the following edge
    SPI1_CTAR0_SLAVE &=~ SPI_CTAR_SLAVE_CPOL_MASK ; //0 The inactive state value of SCK is low.   
   
    SPI1_SR =  SPI_SR_RFDF_MASK 
                    |SPI_SR_RFOF_MASK
                    |SPI_SR_TFFF_MASK
                    |SPI_SR_TFUF_MASK
                    |SPI_SR_TCF_MASK
                    |SPI_SR_EOQF_MASK;
   
    SPI1_RSER|=SPI_RSER_RFDF_RE_MASK;
    //SPI1_MCR &=~ SPI_MCR_HALT_MASK;   
   
}





void SPI1_isr(void)
{
           
char receive_data;
receive_data= (char)SPI1_POPR;
SPI1_SR|= SPI_SR_RFDF_MASK;

SPI1_PUSHR_SLAVE = 0x02;
SPI0_PUSHR = SPI_PUSHR_CONT_MASK |
              SPI_PUSHR_EOQ_MASK  |
              SPI_PUSHR_PCS(1<<0) |(0xff);
while((SPI0_SR & SPI_SR_TCF_MASK)==0);
SPI0_SR |= SPI_SR_TCF_MASK;

}


char hal_spi_transfer_one_byte(char v, char end)
{
    if(end)
        SPI0_PUSHR = SPI_PUSHR_CONT_MASK |
                    SPI_PUSHR_EOQ_MASK  |
                    SPI_PUSHR_PCS(1<<0) |
                    (v);
    else
        SPI0_PUSHR = SPI_PUSHR_CONT_MASK |
                    SPI_PUSHR_PCS(1<<0) |
                    (v);

    while((SPI0_SR & SPI_SR_TCF_MASK)==0);
    SPI0_SR |= SPI_SR_TCF_MASK;
    return SPI0_POPR&0xff;
}

Have a great day,
Ping

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pallenna · ‎03-24-2015

Hi jeremyzhou,

Thanks for your reply, Still am not able to view the transmitted data of slave SPI1. But i see the transmitted data of master SPI0 in the PUSHR register. and what is the problem let me know please help me and i am waiting for your reply.and i did small corrections in the for clock settings.

/*

* File: hello_world.c

* Purpose: Main process

*

*/

#include "common.h"

void SPI0_Master_init(void);

void SPI1_Slave_init(void);

//char hal_spi_transfer_one_byte(char v, char end);

char hal_spi_transfer_one_byte(char value);

void main(void)

{

char r;

SIM_SCGC5 |= ( SIM_SCGC5_PORTA_MASK

| SIM_SCGC5_PORTB_MASK

| SIM_SCGC5_PORTC_MASK

| SIM_SCGC5_PORTD_MASK

| SIM_SCGC5_PORTE_MASK);

//UART5_C2 |= UART_C2_RIE_MASK;//for Receiver Full Interrupt for uart5

//enable_irq(55);//Enable UART5_RX IRQ

SPI0_Master_init();

SPI1_Slave_init();

//Master send 0x01;

SPI0_MCR&=~SPI_MCR_HALT_MASK;

SPI1_MCR&=~SPI_MCR_HALT_MASK;

hal_spi_transfer_one_byte(0x1);

enable_irq(27);//Enable SPI1_ISR

//Waiting for the data from SPI1

while(!(SPI0_SR & SPI_SR_RFDF_MASK));

r=(char)SPI0_POPR;

}

void SPI0_Master_init(void)

{

SIM_SCGC6 |= SIM_SCGC6_DSPI0_MASK;//CLK enable for SPI_0 Module

PORTC_PCR4 &= ~PORT_PCR_MUX_MASK;//PCS0 Select PRIMARY - A69

PORTC_PCR4 |= PORT_PCR_MUX(2);

PORTC_PCR5 &= ~PORT_PCR_MUX_MASK;//SCK Select PRIMARY - A70

PORTC_PCR5 |= PORT_PCR_MUX(2);

PORTC_PCR6 &= ~PORT_PCR_MUX_MASK;//SOUT Select PRIMARY - A71

PORTC_PCR6 |= PORT_PCR_MUX(2);

PORTC_PCR7 &= ~PORT_PCR_MUX_MASK;//SIN Select PRIMARY - A72

PORTC_PCR7 |= PORT_PCR_MUX(2);

SPI0_MCR |= (SPI_MCR_MSTR_MASK|SPI_MCR_HALT_MASK);

SPI0_MCR &= ~SPI_MCR_MDIS_MASK;//Clear module disable bit for SPI clocks

SPI0_MCR |= SPI_MCR_DIS_RXF_MASK |

SPI_MCR_DIS_TXF_MASK |

SPI_MCR_CLR_RXF_MASK |

SPI_MCR_CLR_TXF_MASK;

SPI0_MCR |= SPI_MCR_CONT_SCKE_MASK; //continuous clock

SPI0_MCR |= SPI_MCR_PCSIS(1<<0);

SPI0_CTAR0 &= ~SPI_CTAR_FMSZ_MASK;

SPI0_CTAR0 |= SPI_CTAR_FMSZ(0x7)//Frame Size = 7 + 1

// | SPI_CTAR_DBR_MASK // Duty cycle 50/50

| SPI_CTAR_PBR(0)//BAUD RATE PRESCALER is 2

| SPI_CTAR_BR(0x5); //SCK BAUD RATE = (F_busck/PBR)*[(1+DBR)/BR]

SPI0_CTAR0 &=~ SPI_CTAR_SLAVE_CPHA_MASK ; //Data is captured on the leading edge of SCK and changed on the following edge

SPI0_CTAR0 &=~ SPI_CTAR_SLAVE_CPOL_MASK ; //0 The inactive state value of SCK is low.

SPI0_SR = SPI_SR_RFDF_MASK

| SPI_SR_RFOF_MASK

|SPI_SR_TFFF_MASK

|SPI_SR_TFUF_MASK

|SPI_SR_TCF_MASK

|SPI_SR_EOQF_MASK;

//SPI0_MCR &=~ SPI_MCR_HALT_MASK;

}

void SPI1_Slave_init(void)

{

SIM_SCGC6 |= SIM_SCGC6_DSPI1_MASK;//CLK enable for SPI_1 Module

PORTE_PCR0 &= ~PORT_PCR_MUX_MASK;//PCS0 Select PRIMARY - B22

PORTE_PCR0 |= PORT_PCR_MUX(2);

PORTE_PCR1 &= ~PORT_PCR_MUX_MASK;//SOUT Select PRIMARY - B11

PORTE_PCR1 |= PORT_PCR_MUX(2);

PORTE_PCR2 &= ~PORT_PCR_MUX_MASK;//SCK Select PRIMARY - B7

PORTE_PCR2 |= PORT_PCR_MUX(2);

PORTE_PCR3 &= ~PORT_PCR_MUX_MASK;//SIN Select PRIMARY - B10

PORTE_PCR3 |= PORT_PCR_MUX(2);

SPI1_MCR &=~ SPI_MCR_MSTR_MASK;

SPI1_MCR |= SPI_MCR_HALT_MASK;

SPI1_MCR |= SPI_MCR_PCSIS(1<<0); //The inactive state of PCSx is high.

//SPI1_CTAR0 &= ~SPI_CTAR_FMSZ_MASK;

SPI1_CTAR0_SLAVE |= SPI_CTAR_FMSZ(0x7);//Frame Size = 7 + 1

SPI1_CTAR0_SLAVE &=~ SPI_CTAR_SLAVE_CPHA_MASK ; //Data is captured on the leading edge of SCK and changed on the following edge

SPI1_CTAR0_SLAVE &=~ SPI_CTAR_SLAVE_CPOL_MASK ; //0 The inactive state value of SCK is low.

SPI1_SR = SPI_SR_RFDF_MASK

|SPI_SR_RFOF_MASK

|SPI_SR_TFFF_MASK

|SPI_SR_TFUF_MASK

|SPI_SR_TCF_MASK

|SPI_SR_EOQF_MASK;

SPI1_RSER|=SPI_RSER_RFDF_RE_MASK;

//SPI1_MCR &=~ SPI_MCR_HALT_MASK;

}

void SPI1_isr(void)

{

char receive_data;

receive_data= (char)SPI1_POPR;

SPI1_SR|= SPI_SR_RFDF_MASK;

SPI1_PUSHR_SLAVE = 0x02;

SPI0_PUSHR = SPI_PUSHR_CONT_MASK |

SPI_PUSHR_EOQ_MASK |

SPI_PUSHR_PCS(1<<0) |(0xff);

while((SPI0_SR & SPI_SR_TCF_MASK)==0);

SPI0_SR |= SPI_SR_TCF_MASK;

}

char hal_spi_transfer_one_byte(char value)

{

SPI0_PUSHR = SPI_PUSHR_CONT_MASK |

SPI_PUSHR_EOQ_MASK |

SPI_PUSHR_PCS(1<<0) |

(value);

while((SPI0_SR & SPI_SR_TCF_MASK)==0);

SPI0_SR |= SPI_SR_TCF_MASK;

return SPI0_POPR&0xff;

}

jeremyzhou · ‎03-25-2015

Hi Padmaja,

I'm working on this issue now and I think it may be about pin selection.

I'll try another pins for SPI0, SPI1 and the details as below. You also can have a try.

  /* pin mux */
  PORTA_PCR14 &= ~PORT_PCR_MUX_MASK;
  PORTA_PCR14 |= PORT_PCR_MUX(2); //SPI0_PCS0  //PTC4, PTE16, PTD0
  PORTA_PCR15 &= ~PORT_PCR_MUX_MASK;
  PORTA_PCR15 |= PORT_PCR_MUX(2); //SPI0_SCK    //PTC5, PTD1, PTE17
  PORTA_PCR16 &= ~PORT_PCR_MUX_MASK;
  PORTA_PCR16 |= PORT_PCR_MUX(2); //SPI0_SOUT  //PTC6, PTD2, PTE18
  PORTA_PCR17 &= ~PORT_PCR_MUX_MASK;
  PORTA_PCR17 |= PORT_PCR_MUX(2); //SPI0_SIN    //PTC7, PTD3, PTE19

  PORTB_PCR10 &= ~PORT_PCR_MUX_MASK;
  PORTB_PCR10 |= PORT_PCR_MUX(2); //SPI1_PCS0  //PTE4
  PORTB_PCR11 &= ~PORT_PCR_MUX_MASK;
  PORTB_PCR11 |= PORT_PCR_MUX(2); //SPI1_SCK    //PTE2
  PORTB_PCR16 &= ~PORT_PCR_MUX_MASK;
  PORTB_PCR16 |= PORT_PCR_MUX(2); //SPI1_SOUT  //PTE1, PTE3
  PORTB_PCR17 &= ~PORT_PCR_MUX_MASK;
  PORTB_PCR17 |= PORT_PCR_MUX(2); //SPI1_SIN    //PTE1, PTE3

Have a great day,
Ping

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-----------------------------------------------------------------------------------------------------------------------

pallenna · ‎03-25-2015

Hi jeremyzhou,

Now also i tried with your suggestion but still am not getting anything on the slave register of PUSHR and POPR.

Thanks and Regards,

Padmaja

jeremyzhou · ‎03-26-2015

Hi Padmaja,

I've also try other PORT for SPI communication. It can work and the SPI1 interrupt is available to enter too.

And the update code as below and please refer to it.

#include "common.h"

void SPI0_Master_init(void);
void SPI1_Slave_init(void);
char hal_spi_transfer_one_byte(char v, char end);
char x;

void main(void)
{
    char r;
    SIM_SCGC5 |= (  SIM_SCGC5_PORTA_MASK
                        | SIM_SCGC5_PORTB_MASK
                        | SIM_SCGC5_PORTC_MASK
                        | SIM_SCGC5_PORTD_MASK
                        | SIM_SCGC5_PORTE_MASK);
                 
    //UART5_C2 |= UART_C2_RIE_MASK;//for Receiver Full Interrupt for uart5     
    //enable_irq(55);//Enable UART5_RX IRQ

    SPI0_Master_init();
    SPI1_Slave_init();
    //Master send 0x01;
        SPI0_MCR&=~SPI_MCR_HALT_MASK;
        SPI1_MCR&=~SPI_MCR_HALT_MASK;
        enable_irq(27);//Enable SPI1_ISR
        EnableInterrupts;
        SPI1_PUSHR_SLAVE = 0x0e;
    hal_spi_transfer_one_byte(0x01,0);
     

      /*SPI1_PUSHR_SLAVE |= 0x02;
SPI0_PUSHR = SPI_PUSHR_CONT_MASK
              |SPI_PUSHR_EOQ_MASK
              |SPI_PUSHR_PCS(1<<0) |(0xee);
while((SPI0_SR & SPI_SR_TCF_MASK)==0);
SPI0_SR |= SPI_SR_TCF_MASK;
x =(char)SPI0_POPR&0xff;
out_char(x);*/

        while(1);
    //enable_irq(27);//Enable SPI1_ISR
        //EnableInterrupts;
        //Waiting for the data from SPI1


           
}

void SPI0_Master_init(void)
{
  SIM_SCGC6 |= SIM_SCGC6_DSPI0_MASK;//CLK enable for SPI_0 Module 
  PORTA_PCR14 &= ~PORT_PCR_MUX_MASK;
  PORTA_PCR14 |= PORT_PCR_MUX(2); //SPI0_PCS0  //PTC4, PTE16, PTD0
  PORTA_PCR15 &= ~PORT_PCR_MUX_MASK;
  PORTA_PCR15 |= PORT_PCR_MUX(2); //SPI0_SCK    //PTC5, PTD1, PTE17
  PORTA_PCR16 &= ~PORT_PCR_MUX_MASK;
  PORTA_PCR16 |= PORT_PCR_MUX(2); //SPI0_SOUT  //PTC6, PTD2, PTE18
  PORTA_PCR17 &= ~PORT_PCR_MUX_MASK;
  PORTA_PCR17 |= PORT_PCR_MUX(2); //SPI0_SIN    //PTC7, PTD3, PTE19

  SPI0_MCR |= (SPI_MCR_MSTR_MASK|SPI_MCR_HALT_MASK);

  SPI0_MCR &= ~SPI_MCR_MDIS_MASK;//Clear module disable bit for SPI clocks
  SPI0_MCR |= SPI_MCR_DIS_RXF_MASK |
              SPI_MCR_DIS_TXF_MASK |
              SPI_MCR_CLR_RXF_MASK |
              SPI_MCR_CLR_TXF_MASK;
             
  SPI0_MCR |= SPI_MCR_PCSIS(1<<0);
           
  SPI0_CTAR0 &= ~SPI_CTAR_FMSZ_MASK;
  SPI0_CTAR0 |= SPI_CTAR_FMSZ(0x7)//Frame Size = 7 + 1
          |SPI_CTAR_DBR_MASK // Duty cycle 50/50
          |SPI_CTAR_PBR(0)//BAUD RATE PRESCALER is 2
          |SPI_CTAR_BR(0x03); //SCK BAUD RATE = (F_busck/PBR)*[(1+DBR)/BR] 
  SPI0_SR =  SPI_SR_RFDF_MASK
            |SPI_SR_RFOF_MASK
            |SPI_SR_TFFF_MASK
            |SPI_SR_TFUF_MASK
            |SPI_SR_TCF_MASK
            |SPI_SR_EOQF_MASK;
    //SPI0_MCR &=~ SPI_MCR_HALT_MASK;
}

void SPI1_Slave_init(void)
{
    SIM_SCGC6 |= SIM_SCGC6_DSPI1_MASK;//CLK enable for SPI_1 Module

        PORTB_PCR10 &= ~PORT_PCR_MUX_MASK;
        PORTB_PCR10 |= PORT_PCR_MUX(2); //SPI1_PCS0  //PTE4
        PORTB_PCR11 &= ~PORT_PCR_MUX_MASK;
        PORTB_PCR11 |= PORT_PCR_MUX(2); //SPI1_SCK    //PTE2
        PORTB_PCR16 &= ~PORT_PCR_MUX_MASK;
        PORTB_PCR16 |= PORT_PCR_MUX(2); //SPI1_SOUT  //PTE1, PTE3
        PORTB_PCR17 &= ~PORT_PCR_MUX_MASK;
        PORTB_PCR17 |= PORT_PCR_MUX(2); //SPI1_SIN    //PTE1, PTE3


    SPI1_MCR &=~ SPI_MCR_MSTR_MASK;
        SPI1_MCR &= ~SPI_MCR_MDIS_MASK;//Clear module disable bit for SPI clocks
    SPI1_MCR |= SPI_MCR_HALT_MASK;
    SPI1_MCR |= SPI_MCR_PCSIS(1<<0);    //The inactive state of PCSx is high.
     
        SPI1_MCR |= SPI_MCR_DIS_RXF_MASK |
                    SPI_MCR_DIS_TXF_MASK |
                    SPI_MCR_CLR_RXF_MASK |
                    SPI_MCR_CLR_TXF_MASK;
     
    SPI1_CTAR0 &= ~SPI_CTAR_FMSZ_MASK;       
    SPI1_CTAR0_SLAVE |= SPI_CTAR_FMSZ(0x7);//Frame Size = 7 + 1
    SPI1_CTAR0_SLAVE &=~ SPI_CTAR_SLAVE_CPHA_MASK ; //Data is captured on the leading edge of SCK and changed on the following edge
    SPI1_CTAR0_SLAVE &=~ SPI_CTAR_SLAVE_CPOL_MASK ; //0 The inactive state value of SCK is low. 

    SPI1_SR =  SPI_SR_RFDF_MASK
                    |SPI_SR_RFOF_MASK
                    |SPI_SR_TFFF_MASK
                    |SPI_SR_TFUF_MASK
                    |SPI_SR_TCF_MASK
                    |SPI_SR_EOQF_MASK;

    SPI1_RSER|=SPI_RSER_RFDF_RE_MASK;
    //SPI1_MCR &=~ SPI_MCR_HALT_MASK;       
}





void SPI1_isr(void)
{
         

//receive_data= (char)SPI1_POPR;
SPI1_SR|= SPI_SR_RFDF_MASK;
SPI1_RSER&=~SPI_RSER_RFDF_RE_MASK;



  SPI1_PUSHR_SLAVE = 0;
  SPI1_PUSHR_SLAVE |= 0x03;
  hal_spi_transfer_one_byte(0xff,0);

SPI1_PUSHR_SLAVE |= 0x02;
SPI0_PUSHR = SPI_PUSHR_CONT_MASK
              |SPI_PUSHR_PCS(1<<0) |(0xee);
while((SPI0_SR & SPI_SR_TCF_MASK)==0);
SPI0_SR |= SPI_SR_TCF_MASK;

}


char hal_spi_transfer_one_byte(char v, char end)
{
    if(end)
        SPI0_PUSHR = //SPI_PUSHR_CONT_MASK |
                    SPI_PUSHR_EOQ_MASK  |
                    SPI_PUSHR_PCS(1<<0) |
                    (v);
    else
        SPI0_PUSHR = SPI_PUSHR_CONT_MASK |
                    SPI_PUSHR_PCS(1<<0) |
                    (v);

    while((SPI0_SR & SPI_SR_TCF_MASK)==0);
    SPI0_SR |= SPI_SR_TCF_MASK;
    return (char)SPI0_POPR&0xff;
}

Have a great day,
Ping

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pallenna · ‎04-06-2015

Hi Jeremyzhou,

Thanks for your reply,the program is goes to SPI1_isr but i am not getting the data in the pop register of master of SPI0 and slave of SPI1. when i am debugging the program, the data of master and slave in write register of PUSHR shows data in the Register view , what i am written in the master SPI0_PUSHR register and slave of SPI1_PUSHR_SLAVE and when i am trying to read the data of master and slave in read register of POPR doesn't contains data.for this i tried all possible ways. so please help me.and i had already send code also please once again verify it.please give me reply as soon as possible.

Thanks and Regards

padmaja

jeremyzhou · ‎04-07-2015

Hi Padmaja,

I'd like to shared a simply code about the SPI0 send the 0x01 to SPI1, meanwhile the SPI1 sends the 0x0e to SPI0 and SPI10 would use interrupt mode to receive the data.

Please refer to it for details.

/*
* File:        hello_world.c
* Purpose:        Main process
*
*/

#include "common.h"

void SPI0_Master_init(void);
void SPI1_Slave_init(void);
char hal_spi_transfer_one_byte(char v, char end);
char x;

void main(void)
{
    char r;
    SIM_SCGC5 |= (  SIM_SCGC5_PORTA_MASK
                        | SIM_SCGC5_PORTB_MASK
                        | SIM_SCGC5_PORTC_MASK
                        | SIM_SCGC5_PORTD_MASK
                        | SIM_SCGC5_PORTE_MASK);
                   
   
   
    SPI0_Master_init();
    SPI1_Slave_init();
    //Master send 0x01;
        SPI0_MCR&=~SPI_MCR_HALT_MASK;
        SPI1_MCR&=~SPI_MCR_HALT_MASK;
        enable_irq(27);//Enable SPI1_ISR
        EnableInterrupts;
        SPI1_PUSHR_SLAVE = 0x0e;
    r=hal_spi_transfer_one_byte(0x01,0);
        out_char(r);

        while(1);


   
             
}

void SPI0_Master_init(void)
{
  SIM_SCGC6 |= SIM_SCGC6_DSPI0_MASK;//CLK enable for SPI_0 Module   
  PORTA_PCR14 &= ~PORT_PCR_MUX_MASK;
  PORTA_PCR14 |= PORT_PCR_MUX(2); //SPI0_PCS0  //PTC4, PTE16, PTD0
  PORTA_PCR15 &= ~PORT_PCR_MUX_MASK;
  PORTA_PCR15 |= PORT_PCR_MUX(2); //SPI0_SCK    //PTC5, PTD1, PTE17
  PORTA_PCR16 &= ~PORT_PCR_MUX_MASK;
  PORTA_PCR16 |= PORT_PCR_MUX(2); //SPI0_SOUT  //PTC6, PTD2, PTE18
  PORTA_PCR17 &= ~PORT_PCR_MUX_MASK;
  PORTA_PCR17 |= PORT_PCR_MUX(2); //SPI0_SIN    //PTC7, PTD3, PTE19
   
  SPI0_MCR |= (SPI_MCR_MSTR_MASK|SPI_MCR_HALT_MASK);

  SPI0_MCR &= ~SPI_MCR_MDIS_MASK;//Clear module disable bit for SPI clocks
  SPI0_MCR |= SPI_MCR_DIS_RXF_MASK |
              SPI_MCR_DIS_TXF_MASK |
              SPI_MCR_CLR_RXF_MASK |
              SPI_MCR_CLR_TXF_MASK;
               
  SPI0_MCR |= SPI_MCR_PCSIS(1<<0); 
             
  SPI0_CTAR0 &= ~SPI_CTAR_FMSZ_MASK;
  SPI0_CTAR0 |= SPI_CTAR_FMSZ(0x7)//Frame Size = 7 + 1
          |SPI_CTAR_DBR_MASK // Duty cycle 50/50
          |SPI_CTAR_PBR(0)//BAUD RATE PRESCALER is 2
          |SPI_CTAR_BR(0x03); //SCK BAUD RATE = (F_busck/PBR)*[(1+DBR)/BR]   
  SPI0_SR =  SPI_SR_RFDF_MASK 
            |SPI_SR_RFOF_MASK
            |SPI_SR_TFFF_MASK
            |SPI_SR_TFUF_MASK
            |SPI_SR_TCF_MASK
            |SPI_SR_EOQF_MASK;
    //SPI0_MCR &=~ SPI_MCR_HALT_MASK;
}

void SPI1_Slave_init(void)
{
    SIM_SCGC6 |= SIM_SCGC6_DSPI1_MASK;//CLK enable for SPI_1 Module
   
        PORTB_PCR10 &= ~PORT_PCR_MUX_MASK;
        PORTB_PCR10 |= PORT_PCR_MUX(2); //SPI1_PCS0  //PTE4
        PORTB_PCR11 &= ~PORT_PCR_MUX_MASK;
        PORTB_PCR11 |= PORT_PCR_MUX(2); //SPI1_SCK    //PTE2
        PORTB_PCR16 &= ~PORT_PCR_MUX_MASK;
        PORTB_PCR16 |= PORT_PCR_MUX(2); //SPI1_SOUT  //PTE1, PTE3
        PORTB_PCR17 &= ~PORT_PCR_MUX_MASK;
        PORTB_PCR17 |= PORT_PCR_MUX(2); //SPI1_SIN    //PTE1, PTE3

   
    SPI1_MCR &=~ SPI_MCR_MSTR_MASK;
        SPI1_MCR &= ~SPI_MCR_MDIS_MASK;//Clear module disable bit for SPI clocks
    SPI1_MCR |= SPI_MCR_HALT_MASK;
    SPI1_MCR |= SPI_MCR_PCSIS(1<<0);    //The inactive state of PCSx is high. 
       
        SPI1_MCR |= SPI_MCR_DIS_RXF_MASK |
                    SPI_MCR_DIS_TXF_MASK |
                    SPI_MCR_CLR_RXF_MASK |
                    SPI_MCR_CLR_TXF_MASK;
       
    SPI1_CTAR0 &= ~SPI_CTAR_FMSZ_MASK;         
    SPI1_CTAR0_SLAVE |= SPI_CTAR_FMSZ(0x7);//Frame Size = 7 + 1
    SPI1_CTAR0_SLAVE &=~ SPI_CTAR_SLAVE_CPHA_MASK ; //Data is captured on the leading edge of SCK and changed on the following edge
    SPI1_CTAR0_SLAVE &=~ SPI_CTAR_SLAVE_CPOL_MASK ; //0 The inactive state value of SCK is low.   
   
    SPI1_SR =  SPI_SR_RFDF_MASK 
                    |SPI_SR_RFOF_MASK
                    |SPI_SR_TFFF_MASK
                    |SPI_SR_TFUF_MASK
                    |SPI_SR_TCF_MASK
                    |SPI_SR_EOQF_MASK;
   
    SPI1_RSER|=SPI_RSER_RFDF_RE_MASK;
    //SPI1_MCR &=~ SPI_MCR_HALT_MASK;         
}





void SPI1_isr(void)
{
           
char receive_data;
receive_data= (char)SPI1_POPR;
SPI1_SR|= SPI_SR_RFDF_MASK;
SPI1_RSER&=~SPI_RSER_RFDF_RE_MASK;
  out_char(receive_data);




}


char hal_spi_transfer_one_byte(char v, char end)
{
    if(end)
        SPI0_PUSHR = //SPI_PUSHR_CONT_MASK |
                    SPI_PUSHR_EOQ_MASK  |
                    SPI_PUSHR_PCS(1<<0) |
                    (v);
    else
        SPI0_PUSHR = SPI_PUSHR_CONT_MASK |
                    SPI_PUSHR_PCS(1<<0) |
                    (v);

    while((SPI0_SR & SPI_SR_TCF_MASK)==0);
    SPI0_SR |= SPI_SR_TCF_MASK;
    return (char)SPI0_POPR&0xff;
}

Have a great day,
Ping

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pallenna · ‎04-07-2015

Hi Jeremyzhou,

Thanks for your reply,still i am not able get data from slave of SPI1 to master of SPI0. but when i am debugging the program in register view window contains only 0xFF data instead of original passed data.i have one more doubt about data read.how access the data from master to slave and slave to master.

Thanks and Regards,

padmaja

jeremyzhou · ‎04-07-2015

Hi Pallenna,

It seems weird, on my board, it's works fine and I'd like to recommend that you should use logic analyzer to detect the communication.

I guess maybe some hardware errors cause this issue.

Hope it helps.
Have a great day,
Ping

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

pallenna · ‎04-07-2015

Hi Jeremyzhou,

Thanks for your reply,really i don't known about logic analyzer and how to use this please explain it. if i did any hard ware fault the TX data goes wrong right but the TX data is coming on master side and slave side.

Thanks and Regards,

padmaja

jeremyzhou · ‎04-08-2015

Hi Pallenna,

The logic analyzer is used to capture the wave between SPI communication, and you can use oscilloscope to do this job too.

It will help you to to find the root cause of this issue.
Have a great day,
Ping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------