Hi Grigorii
Thanks for pointing out the SABGREQ bit!
Unfortunately, when trying to use this to stop a mult-block write it is having no effect at the moment.
What I do as a test is set up for 3 block transfers but only make 2 of them. This leaves the SDHC waiting for the third and final block to be sent (after which all would be OK). I then try to stop the transfer (this is always 'between' blocs and not actually "during" a block transfer) by using this bit and hoping to be able to send CMD12 afterwards.
When I set SABGREQ nothing seems to happen; according to its description there should be an effect on PRSSTAT[RTA], PRSSTAT[WTA] and PRSSTAT[CDIHB] but no change is seen. Also, the description says that one must wait for IRQSTATEN[TCSEN] to set to 1, but this bit is already set to '1' - its default value. In fact this looks to be a mistake because IRQSTATEN[TCSEN] is an enable bit and not a status bit - there is a staus bit called BGE (block gap event) in SDHC_IRQSTAT which seems more likely (it remains at '0').
Since there is no reaction to setting SABGREQ I am worried that it may only work when set 'during' a block transfer and not between blocks in the transfer.
This means that presently the SHCD interface is still blocked, waiting for more blocks to be sent, so the CMD12 still cannot be issued!.
Have you been able to get this to work?
Regards
Mark