How do I port USB Host demo for MK22F51212 to MK22FN1MOVLQ12?

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How do I port USB Host demo for MK22F51212 to MK22FN1MOVLQ12?

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rhana
Contributor III

What steps should be taken?

7 Replies

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JCRib
Contributor II

Hi Robert,

I'm having the same problem as you.

Did you manage to get it working?

Are you using the KSDK K22 example? Freescale messed up the K22 part-numbers. Some K22F have IRC48. The rest of them are identical to K21 or K20.

I think that  system_MK22F51212.h and fsl_mcg_features.h needs to be updated.

In the Freedom K22 board example, the clock setup is 4.

#elif (CLOCK_SETUP == 4)

  #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */

  #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */

  /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */

  #define SYSTEM_MCG_C1_VALUE          0x1AU               /* MCG_C1 */

  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */

  #define SYSTEM_MCG_C2_VALUE          0x24U               /* MCG_C2 */

  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */

  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */

  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */

  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */

/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */

  #define SYSTEM_MCG_C5_VALUE          0x01U               /* MCG_C5 */

/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */

  #define SYSTEM_MCG_C6_VALUE          0x46U               /* MCG_C6 */

/* MCG_C7: OSCSEL=0 */

  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */

/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */

  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */

/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */

  #define SYSTEM_SMC_PMCTRL_VALUE      0x60U               /* SMC_PMCTRL */

/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */

  #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */

/* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */

  #define SYSTEM_SIM_CLKDIV2_VALUE     0x09U               /* SIM_CLKDIV2 */

/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */

  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */

/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */

  #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */

I am still finding the correct settings for clock setup...

fsl_mcg_features.h

line 218

#define FSL_FEATURE_MCG_HAS_IRC_48M (1)

#define FSL_FEATURE_MCG_HAS_FCFTRIM (1)

i think it need to be changed to:

#define FSL_FEATURE_MCG_HAS_IRC_48M (0)

#define FSL_FEATURE_MCG_HAS_FCFTRIM (0)


Best regards,

Jose Ribeiro

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JCRib
Contributor II
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Hui_Ma
NXP TechSupport
NXP TechSupport

For both chips belong with same family, if there with no hardware different, the software should be compatible.


Wish it helps.
best regards
Ma Hui

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rhana
Contributor III

There are slight differences in the USB architecture.

A few bits in the register are different, as follows:

USB0_ADDINFO           bits 7-3

USB0_USBTRC0          bits 4-3

The MK22F51212 USB Module has 4 additional registers:

USB0_CLK_RECOVER_CTRL

USB0_CLK_RECOVER_IRC_EN

USB0_CLK_RECOVER_INT_EN

USB0_CLK_RECOVER_INT_STATUS

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Hui_Ma
NXP TechSupport
NXP TechSupport

Hi, Robert,

You are right.

The MK22FN512VDC12 with IRC48M internal oscillator, while MK22FN1M0VLQ12 without IRC48M internal oscillator.

So, the USB module 48MHz clock need from MCG output clock for MK22FN1M0VLQ12.


Wish it helps.
best regards
Ma Hui

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rhana
Contributor III

Hello, thanks for the response.

The 48MHz internal oscillator is not selected for the USB host demo for the MK22F120.

SIM_SOPT2 shows the USB Clock source is going to come from MCGPLLCLK, and likewise the PLL is the MCGPLLCLK clocking source.

pic1.png

MCG_C5 and MCG_C6 indicate the external 8MHz oscillator is divided by 2, then multiplied by 30. Giving 120MHz.

pic2.png

SIM_SCGC4 indicates USBOTG Clock gating is enabled, and SIM_CLKDIV shows a divider output of 2/5,  .. or 48MH, as the USB Clock source.

pic3.png

So, the USB seems to be getting the clock source correctly.

Any other ideas of where I can look?

Thanks.

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Hui_Ma
NXP TechSupport
NXP TechSupport

Hi Robert,

MK22FN1M0VLQ12 USB clock source as below picture shows:

USB.png

From the MCG register setting, the MCGPLLCLK is 120MHz and USB clock with 2/5 divide will get 48MHz clock.

That code setting should will get the correct USB clock.


Wish it helps.
best regards
Ma Hui

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