Hi, I am using Kinetis K60 and i need to interface with a SRAM 512Kx16bit, it have 16bit od data and 20bit of address.

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Hi, I am using Kinetis K60 and i need to interface with a SRAM 512Kx16bit, it have 16bit od data and 20bit of address.

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grazianob
Contributor I

Hi,

I am using Kinetis K60 and i need to interface with a SRAM 512Kx16bit, it have 16bit of data and 20bit of address.

In order to optimize the pin usage I select  CSCRn[BLS]=1

On “K61 Sub-Family Reference Manual, Rev. 2, Dec 2011”  par 33.4.3  there are the suggested connection,  but but this is different from that present in the document AN4393 “Using FlexBus Interface for Kinetis Microcontrollers, Rev. 0, 05/2012”  al par. 2.3

Someone has already occurred which is the correct connection and what signals FB_BEn should be connected to  BHE and BHL of the SRAM with CSCRn[BLS]=1 ?

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Hui_Ma
NXP TechSupport
NXP TechSupport

Hi

Sorry for the K61 reference manual with the incorrect Data-byte alignment and physical connections table for BLS =1.

Customer can refer K60 100MHz updated reference manual about correct info and AN4393 also with the correct info.

K60 100MHz page 735 (Document Number: K60P144M100SF2V2RM     Rev. 2 Jun 2012)

http://cache.freescale.com/files/32bit/doc/ref_manual/K60P144M100SF2V2RM.pdf

Wish it helps.

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47 Views
Hui_Ma
NXP TechSupport
NXP TechSupport

Hi

Sorry for the K61 reference manual with the incorrect Data-byte alignment and physical connections table for BLS =1.

Customer can refer K60 100MHz updated reference manual about correct info and AN4393 also with the correct info.

K60 100MHz page 735 (Document Number: K60P144M100SF2V2RM     Rev. 2 Jun 2012)

http://cache.freescale.com/files/32bit/doc/ref_manual/K60P144M100SF2V2RM.pdf

Wish it helps.

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