Hard fault when setting USB0_CTL |= ODDRST on K60F

[danielcaetano]

Hello,

I'm trying to use the FSL_USB_Stack on Kinetis MK60FN1 both on the TWR module and on a custom board. When initializing the registers for USB I get a CPU Hard Fault on the instruction USB0_CTL |= USB_CTL_ODDRST_MASK;

I tried debugging on Instruction stepping mode and the fault occurs on the instruction ldrb.w r2, which is as seen below.

270 USB0_CTL |= USB_CTL_ODDRST_MASK;
00002e50: ldr r3, [pc, #320] ; (0x2f94 <USB0_Init+384>)
00002e52: ldr r2, [pc, #320] ; (0x2f94 <USB0_Init+384>)
00002e54: ldrb.w r2, [r2, #148] ; 0x94                                    <- this one
00002e58: uxtb r2, r2
00002e5a: orr.w r2, r2, #2
00002e5e: uxtb r2, r2
00002e60: strb.w r2, [r3, #148] ; 0x94

The value of r2 right before execution is 0x40072000, which is the base address for the USB registers. 0x94 is the correct offset to access the USBx_CTL registers.

Can anyone shed some light on what might be causing this issue?

The project files are attached and, as you can see, I already tried writing into that register in another ways, unsuccessfully.

Thanks in advance,

Daniel Caetano

[davidsherman · Accepted solution]

Hard faults when reading or writing peripherals on Kinetis are usually because the bus clock isn't enabled for the peripheral.  Check the SIM module clock gate registers and make sure the bus clock is enabled first.

[danielcaetano]

I found I forgot to set USBFS in SIM_SCGC4. Problem solved. Thank you very much.

[danielcaetano]

Thank you for the answer David.

Right before I attempt the USB0_CTL operation I affect the SIM_CLKDIV2 and the SIM_SOPT2 registers as follows:

/* SIM_CLKDIV2: USBFSDIV=4,USBFSFRAC=1 */
SIM_CLKDIV2 = (uint32_t)((SIM_CLKDIV2 & (uint32_t)~(uint32_t)(
SIM_CLKDIV2_USBFSDIV(0x03)
)) | (uint32_t)(
SIM_CLKDIV2_USBFSDIV(0x04) |
SIM_CLKDIV2_USBFSFRAC_MASK
));
/* SIM_SOPT2: USBFSRC=0,USBF_CLKSEL=1 */
SIM_SOPT2 = (uint32_t)((SIM_SOPT2 & (uint32_t)~(uint32_t)(
SIM_SOPT2_USBFSRC(0x03)
)) | (uint32_t)(
SIM_SOPT2_USBF_CLKSEL_MASK
));

The output of PLL0 is 120MHz, so the settings in CLKDIV should yield 120*2/5=48MHz. In SOPT2 I select the clock source as the output of PLL0.

Am I missing something?