HSADC on KV5x

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HSADC on KV5x

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pietrodicastri
Senior Contributor II

Good morning

I am reading the URM for the processor, the HSADC. I find some settings difficult to understand.

The 41.3.5 HSADC Channel List Register 1 (HSADCx_CLIST1) and the other CLISTn: if the sequential scan is planned I see a sense in having a totally random use of the two ADCA/B so each sample can refer to  ANAn or ANBn, but in parallel mode there is no way to write on SAMPLE0 the value: 1000 Single Ended: ANB0. The rule I extract seems to be: the first SAMPLE0 to SAMPLE7 refer mandatory to the ADCA while the others to the ADCB. This seems to be parallel coerent with HSADCx_SDIS register where the 0 to 7 bits refer to ADCA and the other to ADCB.
Is it correct???

Another question is on page  1024 of the URM Figure 41-3. HSADC Parallel Scan Mode. It is not clear what means SAMPLEn is from ADLST1 or ADLST2. SAMPLEm is from ADLST3 or ADLST4. What are the ADLSTn?

I searched for the string ADLST in chapter 41 no match is found....

The other open question is how to map the input pins to the ANAn ANBn input in all of the figures. The pinout of the processors shows something like HSADC1A _CH11. This is referring to the ANA11 of the the ADCA of the HSADC1, which is selected with the ANA7 logical input in turn through the CH7_SELA[2:0] bits set to 2.

A similar way map the pinout of the processor to the input slots.

Is it correct??

Thank You

Pietro

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3 Replies

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chris_brown
NXP Employee
NXP Employee

Hi Petro,

Regarding your understanding mentioned in the first paragraph, I confirm your understanding is correct.  In parallel mode, SAMPLE0 - SAMPLE7 can only reference converter A samples, and SAMPLE8 - SAMPLE15 can only reference converter B samples.  This is confirmed in section 41.4.4.2.  

In Figure 41-3, ADLST should be replaced with CLIST.  

In reference to your final question, I think the table at the beginning of the HSADC chapter (table 41-1) does a pretty good job of explaining which HSADC internal channels correspond to which external pins / pads.  Specifically, HSADC1A_CH11 would be HSADC1A_CH7[mux 2], as you point out.  Look at that table and let me know if you have any further questions about that subject.  

Thanks,

Chris

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pietrodicastri
Senior Contributor II

Hei Chris

Thank You for the attention.

It is comfortable to have a confirmation, for now I have not the board here so I cannot test anything. 
The perplexities are vanishing now, the table 41-1 just ran out of my attention but it is clear. 
If You can confirm has no value to write in SAMPLE0 the value: 1000 Single Ended: ANB0 in parallel mode, since the sample0 is linked to the converter A. 

Very much thank You

Pietro

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649 Views
chris_brown
NXP Employee
NXP Employee

Hi Pietro,

I can confirm that you *shouldn't* write 1000 Single ended:  ANB0 to SAMPLE0 when using parallel mode. The register would probably allow that value to be written but I cannot tell you what would happen if that value were written in parallel mode.  It may or may not make a conversion at all in that case.  And if it does make a conversion, I couldn't tell you what the results would be.  

Regards,

Chris