GPIO Open Drain: Schematic?

[belskyc]

Hello,

In the Kinetis K60 uP, the general-purpose-input-output (GPIO) port register PORTx_PCRn, bit ODE called "Open Drain Enable" allows the port to be configured with an "Open Drain Output".  Could anyone please explain to me what the significance of Open-Drain is?  Schematically speaking, what does the port look like with the "Open Drain" enabled vs. disabled?  I'm trying to understand when an application would want an Open-Drain output vs. a non-open-drain. 

Thanks and regards,

~

[mjbcswitzerland · Accepted solution]

Hi

I think that a standard open-drain description contains this information:

http://en.wikipedia.org/wiki/Open_collector

Regards

Mark