GPIO Impedance and switch in low power

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GPIO Impedance and switch in low power

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Contributor II

Dear all,

I'm planning to use a MKL17Z256Vxx4 MCU in a extremely low power project. One of the GPIO pins is connected to a switch (which is sometimes on for days and sometimes off for days). Now I'm trying to figure out if I should use an external weaker pull-down or pull-up resistor. One of the things I cannot find is the digital input impedance (only of ADC).

What is the digital input impedance when no internal pull up or down is configured?

Other advise on how to connect a switch in the most power efficient way is welcome.

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Contributor II

Thanks for the very good advises! The switch is on the board itself so no wiring. I only react on the edge of the switch, therefore my concern about the pull resistors. Otherwise I could use the nice idea of watch windows. The applications can be different. Sometimes the switch is switching a few times per hour but sometimes it a few times (or none) per year. So I stay in deepest sleep as possible and wake on the edge.

 

It's nice to see that the pull-up resistor can be that high, nice way to check and links. Although I don't know if the EMI problems gets too high. In this case I think the SPDT is the way to go. Maybe I can also make a SPDT with MOSFETS for the other optional digital input.

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Senior Contributor II

Look up "Bus Keeper" : Bus-holder - Wikipedia which is two inverters and a resistor to hold the last state, which gets rid of pull resistors.   Things can be done with NAND or NOR Set/Reset flip-flop made from a couple of gates to get rid of the resistor and have more switch options.  Have you considered two push buttons rather than one switch?

The environment of your device is important once start using high impedance resistors, false triggering can become a problem in a electrically noisy environment, motors for example.

Also in a switch that is not often moved do not over look the switches *minimum* clearing current and things like board cleaning.  Everyone knows switches have a maximum current handling capability, the opposite end of the current spectrum is rarely though about.  The rating can frequently be found in the switch data sheet or its quality analyses.

In a non-sealed switch the cleaning fluids put a film on the switch and low currents will not clear the film.  A sealed switch overcomes that problem, however it may have a short life if there is any arching (not likely here I guess, again it depends on the environment) without being exposed to air.  Some switches and relays have a pull-off tab to open a vent hole after cleaning.

When going for LONG sleep times try to avoid QFN packages as they can trap flux under them which in turn can gather contaminants with time,  raising the sleep currents as the months pass.  If QFN's can't be avoided make sure there is a clear path for the cleaning fluid ingress and egress, by-pass-caps and such frequently become obstructions to cleaning.

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Senior Contributor III

I see -- so you do need to specifically wake on both edges.  Well then yes, you are looking at SPDT or Mark's high-value pull-resistor, although I again caution you to consider, in that case, surface-insulation-resistance for the whole connection, especially in regard to any potential humidity concerns.

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Senior Contributor III

Increased 'waste current' due to an input-pin at a voltage 'between the hard rails' is also due to partial turn-on of the nominally-off 'FET' of the input stacked-pair.

You don't mention how often you want to look at this switch input, in the larger context of what I assume is 'mostly' sleep-time (nor why the switch couldn't be SPDT, driving directly to either rail).  I would enable a pull-up (or down; in any case opposite to the switch-on state) shortly before each 'look time', and if the switch is OPEN leave such pull 'on' thereafter (to keep the pin biased to rail); if the switch is CLOSED turn it back off.  This does open a 'small window' where the switch would be CLOSED just AFTER that 'look', and then drag said pull-current until the 'next look', so up to one whole 'look cycle' time (unless of course edge-change on this input is a wake-event, prompting you to look right after some debounce).  You will have to decide if this total watt-seconds 'waste' is tolerable, but this avoids any 'leakage tradeoff' decisions for a constant, 'really high' pull resistor --- BTW, said 'leakage tradeoff' will also have to add consideration for PCB surface insulation resistance and/or for other wiring, considering the 'distance' to this switch.

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Specialist V

Hi

The input impedance of GPIO inputs is (very) high but I don't have an actual value for it.

However, when using very low power modes you MUST avoid floating inputs since they will (drastically) increase the current consumption due to noise randomly switching the input stages.

This means that you should enable pull-up or pull-down resistors on inputs (or use external ones) or you should set pins as outputs (driving either '0' or '1').

In your specific case I would recommend disabling the internal pull-up/down (it will cause about 160uA to flow due to the internal value in your worst case) and then use a potentiometer to find the optimal value:

- 1. GPIO leakage is specified as max. 1uA (across all temperatures), which is probably the most interesting parameter for you. It would mean that about 1.5Meg should be a max. value.
- 2. Do this in low leakage mode and ensure that current doesn't start increasing with larger values; if it does it means that noise on the input is the deciding factor (improbable with 1M)
I expect about 1MOhm to be optimal.

See also https://www.youtube.com/watch?v=kWNlsAoMly4 and http://www.utasker.com/kinetis/FRDM-KL27Z.html for complete low power solutions.

Regards

Mark

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