GCC switches for FPU of MK10FX512VMD12

[a_r_f_]

Dear NXP,

which switched should I add to GCC to enable the code using the FPU of MK10FX512VMD12?
I think I've been trying all combinations of -mfloat-abi and -mfpu with all the possible values.

The code compiles, but when I program the device it doesn't start or hangs.

Best regards,
Adam
A.R.f.
http://arf.net.pl

[mjbcswitzerland]

Hi Adam

These are the GCC compiler flags for your part:

-mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mlittle-endian

However make sure that you also enable the FPU (in code) otherwise it will hard-fault when the compiler generated FPU accesses are performed.

CPACR |= (0xf << 20);   // enable access to FPU

Also ensure that any FPU accesses are long word aligned, otherwise it will also fail.

Regards

Mark

http://www.utasker.com/kinetis.html

[a_r_f_]

Hello Mark,

thank you for the answer. In fact, my code does not write anything to

CPACR, so that's the cause of the whole misfortune.

However, I can't find any documentation for this register. Could you,

please, tell me in which document it is described?

I have downloaded: K10P144M120SF3RM and K10P144M120SF3.

I need at least its address (the header file I have doesn't define it),

but I'd like to understand better what's going on. By googling I have

only found that it is "coprocessor access control register", that's not

so much yet.

Also, what does "long word aligned" mean in practice? I use gcc. Should

I perform floating point operations only for literals defined as long

and only data types for which sizeof == sizeof(float)? Or is it not

allowed to use floating point operations for packed structures? Wouldn't

the compiler take care about that for me?

Best regards,

Adam

W dniu 2017-09-25 o 17:30, mjbcswitzerland pisze:

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Re: GCC switches for FPU of MK10FX512VMD12

reply from Mark Butcher

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in /Kinetis Microcontrollers/ - View the full discussion

<https://community.nxp.com/message/946423?commentID=946423&et=watches.email.thread#comment-946423>

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[mjbcswitzerland]

Adam

For information about the core use the ARM web site: http://infocenter.arm.com/help/index.jsp

There you will find:

"7.3.1. Enabling the FPU

Example 7.1 shows an example code sequence for enabling the FPU in both privileged and user modes. The processor must be in privileged mode to read from and write to the CPACR.

Example 7.1.  Enabling the FPU

; CPACR is located at address 0xE000ED88

LDR.W   R0, =0xE000ED88

; Read CPACR

LDR     R1, [R0]

; Set bits 20-23 to enable CP10 and CP11 coprocessors

ORR     R1, R1, #(0xF << 20)

; Write back the modified value to the CPACR

STR     R1, [R0]"

The FPU is a single-precision unit which operates on floats. Floats are 4 bytes in size and it is correct to use the type "float" and then there is no problem.
If however single-precision floating point value are received in byte streams, such as Ethernet, USB or other communication protocols they will be stored in a (byte) buffer. If you then try to use 4 bytes of a buffer that are not aligned to a 4 byte boundary as the input to a FPU operation it will fail.

Therefore simply extract such data and store it as float, then do the operation, and there are no problems. When trying to be as efficient as possible it is possible to cast an address of the location of the value in the byte buffer to a float (assuming byte order is correct) but this MUST be aligned to a 4 byte boundary. This can cause a difference between SW FPU and HW FPU since it may work with SW FPU (since it can operate without alignment on the Cortex-m4) but will start to fail if the HW FPU takes over the same job.

Regards

Mark

[a_r_f_]

Hello Mark,

thank you for the explanation. That was very helpful.

Best regards,

Adam

W dniu 2017-09-25 o 20:20, mjbcswitzerland pisze:

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Re: GCC switches for FPU of MK10FX512VMD12

reply from Mark Butcher

<https://community.nxp.com/people/mjbcswitzerland?et=watches.email.thread>

in /Kinetis Microcontrollers/ - View the full discussion

<https://community.nxp.com/message/946427?commentID=946427&et=watches.email.thread#comment-946427>

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