Freedom Board KL25Z SPI SLAVE sending problem

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Freedom Board KL25Z SPI SLAVE sending problem

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FJankun
Contributor I

Hello,

  I'm trying to send 4 bytes block using SS1_SendBlock() function generated from PE. Problem is, that only first byte from 4 is send with data, rest 3 is 0xFF.

I'm trying to send 1,2,3,4 and i get (repetable):

0x01 0xFF 0xFF 0xFF

500ms delay

0x02 0xFF 0xFF 0xFF

500ms delay

0x03 0xFF 0xFF 0xFF

500ms delay

0x04 0xFF 0xFF 0xFF

500ms delay

 

I'm using CW 10.4 and Freedom Board with KL25Z 1N97F. Do You have any ideas ?

Best Regards

Filip Jankun

 

 

 

5364_5364.pngpastedImage_1.png

Original Attachment has been moved to: SPI_FRDM.zip

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martynhunt
NXP Employee
NXP Employee

Hi Filip,

For the K60 DSPI to drive the CS to idle after each byte transfer, SPIx_PUSHR[CONT] = 0. Check if that bit is zero in your MQX application. Hope that helps.

Best regards,

Martyn

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martynhunt
NXP Employee
NXP Employee

Hi Filip,

From looking at your screenshot of your SPI signals, I see that you are not toggling the SS line after each byte transfer. Unless the slave receives a high SS input after the byte is sent, it will send whatever is present in the SPI data register, which is the received data from the MOSI line. If SPI MOSI is high by default, the slave will transmit 0xFF after the first byte transfer. Let me know if toggling the SS line after each byte transfer solves your issues. Thank you.

Best regards,

Martyn

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FJankun
Contributor I

Hi Martyn,

  You are right. Device that is trying to read from FRDM Board is Kinetis K60 in TOWER and MQX 4.0.1. I don't know why it is not toggling CS after each byte reading. I'll try to divide fread() to single bytes and let You know how it works.

Best Regards

Filip Jankun

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martynhunt
NXP Employee
NXP Employee

Hi Filip,

For the K60 DSPI to drive the CS to idle after each byte transfer, SPIx_PUSHR[CONT] = 0. Check if that bit is zero in your MQX application. Hope that helps.

Best regards,

Martyn

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FJankun
Contributor I

Hi Martyn,

  thank You for Your help. Where in KL25Z documentation is mentioned that each SPI byte has to be separated with CS idle state ?

Best Regards

Filip Jankun

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martynhunt
NXP Employee
NXP Employee

Hi Filip,

Glad I could help! As far as where in the documentation, section 37.4.5 'SPI Clock Formats' of the KL25 Reference Manual explains that SS must go high after each transfer for SPIx_C1[CPHA] = 0.

Best regards,

Martyn

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