Flexcan mailboxes

[davidsherman]

I'm getting confused by the FlexCAN documentation.  This is for a KE18F part.  The documentation says that there are 16 message buffers, but 64 mailboxes.  If I'm using the Rx FIFO, then message buffers 0-7 are not available.  The confusing part is that it seems to use the terms "Message Buffer", "Mailbox", and "MB" interchangeably.  What do mailboxes 17-64 represent then, and what are they used for?

[davidsherman]

Thanks, I think I understand now.  It was just a little confusing because the documentation implied it had up to 63 mailboxes, but only 16 message buffers.  Looks like once it gets past 16 the space is unreadable.

[egoodii]

Those terms are indeed generally interchangeable.  I can't find any particular information on these KE1x parts, most specifically a Reference Manual.  BUT I assume said documentation will be like 'most others' for Kinetis, in which the 'FlexCAN peripheral' documentation section will be the 'full, possible capabilities' of the peripheral-module as designed (which includes address and configuration-space 'options' for 64 mailboxes/message-buffers), whereas there will be a paragraph in Chapter 3 (Chip Configuration) under a CAN configuration block saying how the peripheral was instantiated for this particular silicon.  You should find a heading something like Number of message buffers, and for the chips I have used that has been 16 total (so '8' for RX FIFO, 8 for TX MBs and/or additional ID filters).  From K22P80M120SF5V2RM:

3.9.2.2 Number of message buffers

Each FlexCAN module contains 16 message buffers. Each message buffer is 16 bytes.

So I think we can say 17-64 'do not exist' on your part, and all reference to them, or filter-functions that might use said memory-areas (as set from RFFN, for instance), are 'simply confusing at best'.

[davidsherman]

OK, I'm looking at the reference manual you mentioned, but it is similar in that it says there are 16 message buffers, from 0x80 to 0x17F in the memory map.  But, if you look at the message buffer structure, it says the memory area from 0x80 to 0x47C is used by the Mailboxes.  So is the RAM from 0x180 to 0x470C in this case just empty RAM?

[egoodii]

More likely 'non existent RAM' (and may even give a busfault if access is attempted).  Which is to say that when the macro-block parameters are brought into the silicon-compiler, it creates only enough RAM/space for the called-for 16 MBs.  Take this note for instance under RFFN:

(SETUP_MB - 6) × 4

where SETUP_MB is the least between NUMBER_OF_MB and MAXMB.

The number of remaining Mailboxes available will be:

(SETUP_MB - 8) - (RFFN × 2)

If the Number of Rx FIFO Filters programmed through RFFN exceeds the SETUP_MB value

(memory space available) the exceeding ones will not be functional.

The 'message buffer structure' diagram will call out the 'maximum possible' per the architecture design, with probably a 'footnote' about NUMBER_OF_MB, 16 in these cases.

[michael_galda]

Hi, I looked into this thread yesterday. But Earl was faster providing the correct answer.

Yes, the CAN module itself can provide "up-to" 1kB of RAM, which can be used for Message Buffers.

- But the real size of the RAM implemented can vary (for different devices). The max size should be specified in the Reference Manual.

- In most of the cases the RAM above size specified in RM is unexisting (unimplemented) - to save the space on the silicon.

But earlier, I met the cases, where complete 1kB RAM block has been implemented (so the RAM unused by CAN MB, can be used by user to for instance).

It can be tested very easily:

- for instance by writing a pattern (0xAA, 0x55) to the RAM location inside the CAN module MB memory range. If the area is writable, the RAM is implemented.

- Writing to this location from the SW code will result to the "bus-fault exception", when the RAM cell is not implemented on the specific location.