Flexbus on K66F

[a8Chcx]

Hi,

I am using K66F to access external flash(32M) and SDRAM(32M) in no-multiplex mode.

1) Here are pin mux:

void BOARD_InitPins(void)

{

CLOCK_EnableClock(kCLOCK_PortA); /* Port A Clock Gate Control: Clock enabled */

CLOCK_EnableClock(kCLOCK_PortB); /* Port B Clock Gate Control: Clock enabled */

CLOCK_EnableClock(kCLOCK_PortC); /* Port C Clock Gate Control: Clock enabled */

CLOCK_EnableClock(kCLOCK_PortD); /* Port D Clock Gate Control: Clock enabled */

CLOCK_EnableClock(kCLOCK_PortE); /* Port E Clock Gate Control: Clock enabled */

//-----*****Just doing re-arrangement from pin_mux.c that is generated by pin tool*****-----

//-----*****UART0 used as DEBUG interface on Demo Board*****-----

// PORT_SetPinMux(PORTB, PIN16_IDX, kPORT_MuxAlt3); /* PORTB16 (pin E10) is configured as UART0_RX(Demo Board) */

// PORT_SetPinMux(PORTB, PIN17_IDX, kPORT_MuxAlt3); /* PORTB17 (pin E9) is configured as UART0_TX(Demo Board) */

//----Configured on iNetVu 7710 Version 5.0

//-----*****UART1 used as DEBUG interface*****-----

PORT_SetPinMux(PORTE, PIN0_IDX, kPORT_MuxAlt3); /* PORTE0 (pin 1) is configured as UART1_TX */

PORT_SetPinMux(PORTE, PIN1_IDX, kPORT_MuxAlt3); /* PORTE1 (pin 2) is configured as UART1_RX */

//-----*****Configure UART3*****-----

PORT_SetPinMux(PORTE, PIN4_IDX, kPORT_MuxAlt3); /* PORTE4 (pin 7) is configured as UART3_TX */

PORT_SetPinMux(PORTE, PIN5_IDX, kPORT_MuxAlt3); /* PORTE5 (pin 8) is configured as UART3_RX */

//-----*****Configure LPUART0*****-----

PORT_SetPinMux(PORTE, PIN8_IDX, kPORT_MuxAlt5); /* PORTE8 (pin 11) is configured as LPUART0_TX */

PORT_SetPinMux(PORTE, PIN9_IDX, kPORT_MuxAlt5); /* PORTE9 (pin 12) is configured as LPUART0_RX */

//-----*****ENET Configuration*****-----

PORT_SetPinMux(PORTA, PIN12_IDX, kPORT_MuxAlt4); /* PORTA12 (pin 64) is configured as RMII0_RXD1 */

PORT_SetPinMux(PORTA, PIN13_IDX, kPORT_MuxAlt4); /* PORTA13 (pin 65) is configured as RMII0_RXD0 */

PORT_SetPinMux(PORTA, PIN14_IDX, kPORT_MuxAlt4); /* PORTA14 (pin 66) is configured as RMII0_CRS_DV */

PORT_SetPinMux(PORTA, PIN15_IDX, kPORT_MuxAlt4); /* PORTA15 (pin 67) is configured as RMII0_TXEN */

PORT_SetPinMux(PORTA, PIN16_IDX, kPORT_MuxAlt4); /* PORTA16 (pin 68) is configured as RMII0_TXD0 */

PORT_SetPinMux(PORTA, PIN17_IDX, kPORT_MuxAlt4); /* PORTA17 (pin 69) is configured as RMII0_TXD1 */

PORT_SetPinMux(PORTA, PIN5_IDX, kPORT_MuxAlt4); /* PORTA5 (pin 55) is configured as RMII0_RXER */

// On Demo Board

// PORT_SetPinMux(PORTB, PIN0_IDX, kPORT_MuxAlt4); /* PORTB0 (pin H10) is configured as RMII0_MDIO */

// PORTB->PCR[0] = ((PORTB->PCR[0] & (~(PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK))) /* Mask bits to zero which are setting */

// | PORT_PCR_ODE(PCR_ODE_ENABLED) /* Open Drain Enable: Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. */

// );

// PORT_SetPinMux(PORTB, PIN1_IDX, kPORT_MuxAlt4); /* PORTB1 (pin H9) is configured as RMII0_MDC */

//----Configured on iNetVu 7710 Version 5.0

PORT_SetPinMux(PORTA, PIN7_IDX, kPORT_MuxAlt5); /* PORTA7 (pin 59) is configured as RMII0_MDIO */

PORTA->PCR[7] = ((PORTB->PCR[7] & (~(PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK))) /* Mask bits to zero which are setting(ISF, ODE) */

| PORT_PCR_ODE(PCR_ODE_ENABLED) /* Open Drain Enable: Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. */

);

　

//-----*****Initialize the SDRAMC pins*****-----

PORT_SetPinMux(PORTA, PIN6_IDX, kPORT_MuxAlt5); /* PORTA6 (pin 58) is configured as CLKOUT */

// Configured for RMII Network on Demo Board

PORT_SetPinMux(PORTB, PIN0_IDX, kPORT_MuxAlt5); /* PORTB0 (pin 81) is configured as SDRAM_CAS_b---Configured for RMII Network on Demo Board */

PORT_SetPinMux(PORTB, PIN1_IDX, kPORT_MuxAlt5); /* PORTB1 (pin 82) is configured as SDRAM_RAS_b---Configured for RMII Network on Demo Board */

PORT_SetPinMux(PORTB, PIN2_IDX, kPORT_MuxAlt5); /* PORTB2 (pin 83) is configured as SDRAM_WE */

PORT_SetPinMux(PORTB, PIN3_IDX, kPORT_MuxAlt5); /* PORTB3 (pin 84) is configured as SDRAM_CS0_b */

PORT_SetPinMux(PORTB, PIN4_IDX, kPORT_MuxAlt5); /* PORTB4 (pin 85) is configured as SDRAM_CS1_b */

　

// Configure SDRAM Data Pins

PORT_SetPinMux(PORTB, PIN20_IDX, kPORT_MuxAlt5); /* PORTB20 (pin 99) is configured as FB_AD31, SDRAM_D31 */

PORT_SetPinMux(PORTB, PIN21_IDX, kPORT_MuxAlt5); /* PORTB21 (pin 100) is configured as FB_AD30, SDRAM_D30 */

PORT_SetPinMux(PORTB, PIN22_IDX, kPORT_MuxAlt5); /* PORTB22 (pin 101) is configured as FB_AD29, SDRAM_D29 */

PORT_SetPinMux(PORTB, PIN23_IDX, kPORT_MuxAlt5); /* PORTB23 (pin 102) is configured as FB_AD28, SDRAM_D28 */

PORT_SetPinMux(PORTC, PIN12_IDX, kPORT_MuxAlt5); /* PORTC12 (pin 117) is configured as FB_AD27, SDRAM_D27 */

PORT_SetPinMux(PORTC, PIN13_IDX, kPORT_MuxAlt5); /* PORTC13 (pin 118) is configured as FB_AD26, SDRAM_D26 */

PORT_SetPinMux(PORTC, PIN14_IDX, kPORT_MuxAlt5); /* PORTC14 (pin 119) is configured as FB_AD25, SDRAM_D25 */

PORT_SetPinMux(PORTC, PIN15_IDX, kPORT_MuxAlt5); /* PORTC15 (pin 120) is configured as FB_AD24, SDRAM_D24 */

PORT_SetPinMux(PORTB, PIN6_IDX, kPORT_MuxAlt5); /* PORTB6 (pin 87) is configured as FB_AD23, SDRAM_D23 */

PORT_SetPinMux(PORTB, PIN7_IDX, kPORT_MuxAlt5); /* PORTB7 (pin 88) is configured as FB_AD22, SDRAM_D22 */

PORT_SetPinMux(PORTB, PIN8_IDX, kPORT_MuxAlt5); /* PORTB8 (pin 89) is configured as FB_AD21, SDRAM_D21 */

PORT_SetPinMux(PORTB, PIN9_IDX, kPORT_MuxAlt5); /* PORTB9 (pin 90) is configured as FB_AD20, SDRAM_D20 */

PORT_SetPinMux(PORTB, PIN10_IDX, kPORT_MuxAlt5); /* PORTB10 (pin 91) is configured as FB_AD19, SDRAM_D19 */

PORT_SetPinMux(PORTB, PIN11_IDX, kPORT_MuxAlt5); /* PORTB11 (pin 92) is configured as FB_AD18, SDRAM_D18 */

//-----*****UART0 used as DEBUG interface on Demo Board*****-----

PORT_SetPinMux(PORTB, PIN16_IDX, kPORT_MuxAlt5); /* PORTB16 (pin 95) is configured as FB_AD17, SDRAM_D17---Used as DEBUG interface on Demo Board */

PORT_SetPinMux(PORTB, PIN17_IDX, kPORT_MuxAlt5); /* PORTB17 (pin 96) is configured as FB_AD16, SDRAM_D16---Used as DEBUG interface on Demo Board */

// Configure SDRAM Address

PORT_SetPinMux(PORTB, PIN18_IDX, kPORT_MuxAlt5); /* PORTB18 (pin 97) is configured as SDRAM_A23, FB_AD15 */

PORT_SetPinMux(PORTC, PIN0_IDX, kPORT_MuxAlt5); /* PORTC0 (pin 103) is configured as SDRAM_A22, FB_AD14 */

PORT_SetPinMux(PORTC, PIN1_IDX, kPORT_MuxAlt5); /* PORTC1 (pin 104) is configured as SDRAM_A21, FB_AD13 */

PORT_SetPinMux(PORTC, PIN2_IDX, kPORT_MuxAlt5); /* PORTC2 (pin 105) is configured as SDRAM_A20, FB_AD12 */

PORT_SetPinMux(PORTC, PIN4_IDX, kPORT_MuxAlt5); /* PORTC4 (pin 109) is configured as SDRAM_A19, FB_AD11 */

PORT_SetPinMux(PORTC, PIN5_IDX, kPORT_MuxAlt5); /* PORTC5 (pin 110) is configured as SDRAM_A18, FB_AD10 */

PORT_SetPinMux(PORTC, PIN6_IDX, kPORT_MuxAlt5); /* PORTC6 (pin 111) is configured as SDRAM_A17, FB_AD9 */

PORT_SetPinMux(PORTC, PIN7_IDX, kPORT_MuxAlt5); /* PORTC7 (pin 112) is configured as SDRAM_A16, FB_AD8 */

PORT_SetPinMux(PORTC, PIN8_IDX, kPORT_MuxAlt5); /* PORTC8 (pin 113) is configured as SDRAM_A15, FB_AD7 */

PORT_SetPinMux(PORTC, PIN9_IDX, kPORT_MuxAlt5); /* PORTC9 (pin 114) is configured as SDRAM_A14, FB_AD6 */

PORT_SetPinMux(PORTC, PIN10_IDX, kPORT_MuxAlt5); /* PORTC10 (pin 115) is configured as SDRAM_A13, FB_AD5 */

PORT_SetPinMux(PORTD, PIN2_IDX, kPORT_MuxAlt5); /* PORTD2 (pin 129) is configured as SDRAM_A12, FB_AD4 */

PORT_SetPinMux(PORTD, PIN3_IDX, kPORT_MuxAlt5); /* PORTD3 (pin 130) is configured as SDRAM_A11, FB_AD3 */

PORT_SetPinMux(PORTD, PIN4_IDX, kPORT_MuxAlt5); /* PORTD4 (pin 131) is configured as SDRAM_A10, FB_AD2 */

PORT_SetPinMux(PORTD, PIN5_IDX, kPORT_MuxAlt5); /* PORTD5 (pin 132) is configured as SDRAM_A9, FB_AD1 */

// Configure SDRAM Control signal

PORT_SetPinMux(PORTD, PIN7_IDX, kPORT_MuxAlt5); /* PORTD7 (pin 136) is configured as SDRAM_CKE */

PORT_SetPinMux(PORTC, PIN17_IDX, kPORT_MuxAlt5); /* PORTC17 (pin 124) is configured as SDRAM_DQM3 */

PORT_SetPinMux(PORTC, PIN16_IDX, kPORT_MuxAlt5); /* PORTC16 (pin 123) is configured as SDRAM_DQM2 */

PORT_SetPinMux(PORTC, PIN18_IDX, kPORT_MuxAlt5); /* PORTC18 (pin 125) is configured as SDRAM_DQM1 */

PORT_SetPinMux(PORTC, PIN19_IDX, kPORT_MuxAlt5); /* PORTC19 (pin 126) is configured as SDRAM_DQM0 */

//-----*****Configure Flexbus high address*****-----

PORT_SetPinMux(PORTA, PIN28_IDX, kPORT_MuxAlt6); /* PORTA28 (pin 79) is configured as FB_A25 */

PORT_SetPinMux(PORTA, PIN29_IDX, kPORT_MuxAlt6); /* PORTA29 (pin 80) is configured as FB_A24 */

PORT_SetPinMux(PORTD, PIN15_IDX, kPORT_MuxAlt6); /* PORTD15 (pin 144) is configured as FB_A23 */

PORT_SetPinMux(PORTD, PIN14_IDX, kPORT_MuxAlt6); /* PORTD14 (pin 143) is configured as FB_A22 */

PORT_SetPinMux(PORTD, PIN13_IDX, kPORT_MuxAlt6); /* PORTD13 (pin 142) is configured as FB_A21 */

PORT_SetPinMux(PORTD, PIN12_IDX, kPORT_MuxAlt6); /* PORTD12 (pin 141) is configured as FB_A20 */

PORT_SetPinMux(PORTD, PIN11_IDX, kPORT_MuxAlt6); /* PORTD11 (pin 140) is configured as FB_A19 */

PORT_SetPinMux(PORTD, PIN10_IDX, kPORT_MuxAlt6); /* PORTD10 (pin 139) is configured as FB_A18 */

PORT_SetPinMux(PORTD, PIN9_IDX, kPORT_MuxAlt6); /* PORTD9 (pin 138) is configured as FB_A17 */

PORT_SetPinMux(PORTD, PIN8_IDX, kPORT_MuxAlt6); /* PORTD8 (pin 137) is configured as FB_A16 */

// Configure Flexbus RW, OE, chip select and etc Control signal

PORT_SetPinMux(PORTB, PIN19_IDX, kPORT_MuxAlt5); /* PORTB19 (pin 98) is configured as FB_OE_b */

PORT_SetPinMux(PORTC, PIN11_IDX, kPORT_MuxAlt5); /* PORTC11 (pin 116) is configured as FB_RW_b */

PORT_SetPinMux(PORTD, PIN0_IDX, kPORT_MuxAlt5); /* PORTD0 (pin 127) is configured as FB_CS1_b */

PORT_SetPinMux(PORTD, PIN1_IDX, kPORT_MuxAlt5); /* PORTD1 (pin 128) is configured as FB_CS0_b */

//-----The initialization done by tool generation

// Select RMII clock src.

SIM->SOPT2 = ((SIM->SOPT2 & (~(SIM_SOPT2_RMIISRC_MASK))) | SIM_SOPT2_RMIISRC(SOPT2_RMIISRC_ENET)); // Bit19==1---RMII clock source select: External bypass clock (ENET_1588_CLKIN).

SIM->SOPT5 = ((SIM->SOPT5 &

(~(SIM_SOPT5_UART1TXSRC_MASK | SIM_SOPT5_LPUART0TXSRC_MASK))) /* Mask bits to zero which are setting */

| SIM_SOPT5_UART1TXSRC(SOPT5_UART1TXSRC_UART_TX) /* UART 1 transmit data source select: UART1_TX pin */

| SIM_SOPT5_LPUART0TXSRC(SOPT5_LPUART0TXSRC_LPUART_TX) /* LPUART0 transmit data source select: LPUART0_TX pin */

);

SIM->USBPHYCTL = ((SIM->USBPHYCTL &

(~(SIM_USBPHYCTL_USBVREGSEL_MASK))) /* Mask bits to zero which are setting */

| SIM_USBPHYCTL_USBVREGSEL(USBPHYCTL_USBVREGSEL_VREG_IN0) /* Selects the default input voltage source to the USB Regulator in case both VREG_IN0 and VREG_IN1 are powered. If only one of the regulator inputs is powered, it will automatically be selected by the regulator's power mux circuitry.: VREG_IN0 will be selected if both regulator inputs are powered */

);

2) Based on above pin mux. It works fine with SDRAM interface, but I can't access external flash on flexbus.

Here are the initialization for Flexbus.

int32_t *p_mram = (int32_t *)MRAM_START_ADDRESS; // 0x60000000

//-----*****Copied from Httpsrv demo*****-----

struct netif fsl_netif0;

ip4_addr_t fsl_netif0_ipaddr, fsl_netif0_netmask, fsl_netif0_gw;

MPU_Type *base = MPU; //-----*****Copied from Httpsrv demo*****-----

BOARD_InitPins();

BOARD_BootClockRUN();

BOARD_InitDebugConsole();

//-----*****Copied from Httpsrv demo*****-----

// Disable MPU.

base->CESR &= ~MPU_CESR_VLD_MASK;

/* Set clock out to flexbus CLKOUT. */

CLOCK_SetClkOutClock(0); // Bit7:5---Select clock on CLKOUT pin(000---Flexbus CLOCK)

//-----*****SDRAM demo---Sets the Flexbus security level*****-----

soptReg = SIM->SOPT2 & ~SIM_SOPT2_FBSL_MASK;

SIM->SOPT2 = soptReg | SIM_SOPT2_FBSL(3); //Bit9:8==11---Off-chip instruction accesses and data accesses are allowed

　

//-----Copied from Flexbus driver demo-----

/*

* Initialize configurations for MRAM.

* Refer application note: AN4393.

*/

/* Get default config */

/*

* flexbusUserConfig.writeProtect = 0;

* flexbusUserConfig.burstWrite = 0;

* flexbusUserConfig.burstRead = 0;

* flexbusUserConfig.byteEnableMode = 0;

* flexbusUserConfig.autoAcknowledge = true;

* flexbusUserConfig.extendTransferAddress = 0;

* flexbusUserConfig.secondaryWaitStates = 0;

* flexbusUserConfig.byteLaneShift = kFLEXBUS_NotShifted;

* flexbusUserConfig.writeAddressHold = kFLEXBUS_Hold1Cycle;

* flexbusUserConfig.readAddressHold = kFLEXBUS_Hold1Or0Cycles;

* flexbusUserConfig.addressSetup = kFLEXBUS_FirstRisingEdge;

* flexbusUserConfig.portSize = kFLEXBUS_1Byte;

* flexbusUserConfig.group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE;

* flexbusUserConfig.group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4;

* flexbusUserConfig.group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5;

* flexbusUserConfig.group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST;

* flexbusUserConfig.group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA;

*/

FLEXBUS_GetDefaultConfig(&flexbusUserConfig);

/* Configure some parameters when using MRAM */

flexbusUserConfig.waitStates = 6U; /* Wait 6 states for External flash*/

// 0x6000_0000~~0x61FF_0000 for 32M flash, 0x6200_0000~~0x63FF_0000 for IO input/Output

 flexbusUserConfig.chipBaseAddressMask = 0x03FFU; /* 32 Mbytes memory size==0x200U * 64K + A25 as GPIO*/

// Done in FLEXBUS_GetDefaultConfig(&flexbusUserConfig);

flexbusUserConfig.portSize = kFLEXBUS_2Bytes; /* 2 bytes port size(16-bit) of transfer */

flexbusUserConfig.group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_CS1; // kFLEXBUS_MultiplexGroup1_FB_ALE; /* FB_ALE */

flexbusUserConfig.group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_BE_31_24; //kFLEXBUS_MultiplexGroup2_FB_CS4; /* FB_CS4 */

flexbusUserConfig.group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_BE_23_16; //kFLEXBUS_MultiplexGroup3_FB_CS5; /* FB_CS5 */

flexbusUserConfig.group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_BE_15_8; //kFLEXBUS_MultiplexGroup4_FB_TBST; /* FB_TBST */

flexbusUserConfig.group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_BE_7_0; //kFLEXBUS_MultiplexGroup5_FB_TA; /* FB_TA */

PRINTF("\r\nInitialize FLEXBUS.\r\n");

//-----*****Initialize and configure FLEXBUS module*****-----

FLEXBUS_Init(FB, &flexbusUserConfig); // FB_BASE==0x4000_C000

//-----*****FlexBus Testing!!!*****-----

PRINTF("\r\nStart write/read MRAM.\r\n");

PRINTF("\r\n IO_00=0x%x_0x%x_0x%x_0x%x_0x%x\r\n", p_mram, *(uint16_t *)(p_mram + 0x02000000), *(uint16_t *)(p_mram + 0x00010004), *(uint16_t *)(p_mram + 0x00010008), *(uint16_t *)(p_mram + 0x0001000C));

.....

3. I can't access the address above 0x6200_0000(above 16M). Why?

Thanks,

Christie

[Hui_Ma]

Hi,

I checked below code with incorrect info:

// 0x6000_0000~~0x61FF_0000 for 32M flash, 0x6200_0000~~0x63FF_0000 for IO input/Output

 flexbusUserConfig.chipBaseAddressMask = 0x03FFU; /* 32 Mbytes memory size==0x200U * 64K + A25 as GPIO*/

For the MRAM size is 32KB, the [BAM] of  Chip Select Mask Register (FB_CSMRn) is 0x1FF.

Another issue is the MRAM's chip select, I could find the K66's PTD1 lable is #CS0, while I checked M29W256GH's CS# connects with #CE. For you provide the pdf version schematics couldn't do a search, if that chip select signal is connected?

Thank you for the attention.

Have a great day,
Ma Hui

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[a8Chcx]

Hi Hui,

I am using 32M external flash(M29W256GH). The address is 0x6000_0000~~0x61FF_FFFF. Then I am trying to use next 32M for IO part. The address id 0x6200_0000~~0x63FF_0000. So, I need to set MASK=0x03FF, right?

I am using #CS0 or A25--->#CE for flash memory. And #CS0 or #A25 to generate GPIO selection.

For now, I can't access the address 0x6200_000~~0x63FF_0000 when I do the above setting.

Could you tell me how to access the above address and how to set BA and MASK?

Thanks,

Christie

[Hui_Ma]

Hi Christie,

As you mentioned the memory address [0x6200_0000~~0x63FF_0000] is for IO part. Is IO part a FPGA device? Is that device also using the FB_CS0 as chip select? Could you guide which device is IO part at your schematics?

I think the root cause at Flexbus module registers setting.

best regards,

Ma Hui

[a8Chcx]

Hi Hui,

1) I am using CSN1==0x6200_0004 to control U7 and U11. Now it works fine. I can control 16 bit output by using the following:

*(volatile uint16_t *)K66F_IO_CSN1 = 0xFFEF; // D20---Beep 

2) I am using CSN2==0x6200_0008 to read U4 and U5 by using following:

key_pad = *(volatile uint16_t *)K66F_IO_CSN2;

I cab only read low 8-bit, not high 8-bit data, why?

3) When I am trying to read flash (0x6000_0000), I am always get low 8-bit(0xff), not high 8-bit.

uint8_t *p_flash = (uint8_t *)M29W256_FLASH_ADDRESS;

PRINTF("\r\n IO_00=0x%x_0x%x_0x%x_0x%x_0x%x\r\n", p_flash, *(uint16_t *)(p_flash + 1), *(uint16_t *)(p_flash + 2), *(uint16_t *)(p_flash + 3), *(uint16_t *)(p_flash + 3));

Could you tell me where I am wrong to read?

Thanks,

Christie

[Hui_Ma]

About the question 3, your code just read 1 byte:

uint8_t *p_flash = (uint8_t *)M29W256_FLASH_ADDRESS;

Please using uint16_t instead of uint8_t of previous code.

About question 2, the U4 and U5 device's CLK signal connects with CLKOUT, while U7 & U11 device's CLK signal connects with CSN1. If the circuit design could affect the result?

Have a great day,
Ma Hui

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[a8Chcx]

Hi Hui,

I checked the demo code and didn't set flexbus security:

soptReg = SIM->SOPT2 & ~SIM_SOPT2_FBSL_MASK;

SIM->SOPT2 = soptReg | SIM_SOPT2_FBSL(3); //Bit9:8==11---Off-chip instruction accesses and data accesses are allowed

 Is it OK if not set FBSL to access flexbus?

I added the above code and the same result...

Thanks,

Christie