Flexbus configuration

[alex_br]

Could you please help me with flexbus configuration and SRAM ? I am not sure what I am missing? Thanks.

//Set Base address  FB_CSAR2 = (uint32)&MRAM_START_ADDRESS;
  FB_CSCR2  =   FB_CSCR_AA_MASK               | FB_CSCR_WS(1)               | FB_CSCR_PS(2)               | FB_CSCR_BEM_MASK               | FB_CSCR_RDAH(1)               | FB_CSCR_ASET(1)              ; 

  FB_CSMR2  =   FB_CSMR_BAM(0x07) //Set base address mask for 512K address space              | FB_CSMR_V_MASK    //Enable cs signal              ;                //enable BE signals - note, not used in this example  FB_CSPMCR =  FB_CSPMCR_GROUP2(2) | FB_CSPMCR_GROUP3(2);
  //fb clock divider 2  SIM_CLKDIV1 |= SIM_CLKDIV1_OUTDIV3(0x1);     PORTA_PCR28=PORT_PCR_MUX(6);          //fb_ad[25]  PORTA_PCR29=PORT_PCR_MUX(6);          //fb_ad[24]    PORTB_PCR6=PORT_PCR_MUX(5);          //fb_d[7]  PORTB_PCR7=PORT_PCR_MUX(5);          //fb_d[6]  PORTB_PCR8=PORT_PCR_MUX(5);          //fb_d[5]  PORTB_PCR9=PORT_PCR_MUX(5);          //fb_d[4]  PORTB_PCR10=PORT_PCR_MUX(5);         //fb_d[3]    PORTB_PCR11=PORT_PCR_MUX(5);          //fb_d[2]    PORTB_PCR16=PORT_PCR_MUX(5);          //fb_d[1]  PORTB_PCR17=PORT_PCR_MUX(5);          //fb_d[0]    PORTB_PCR18=PORT_PCR_MUX(5);          //fb_ad[15]    PORTB_PCR20=PORT_PCR_MUX(5);          //fb_d[15]    PORTB_PCR21=PORT_PCR_MUX(5);          //fb_d[14]  PORTB_PCR22=PORT_PCR_MUX(5);          //fb_d[13]  PORTB_PCR23=PORT_PCR_MUX(5);          //fb_d[12]      PORTC_PCR0=PORT_PCR_MUX(5);          //fb_ad[14]  PORTC_PCR1=PORT_PCR_MUX(5);          //fb_ad[13]  PORTC_PCR2=PORT_PCR_MUX(5);          //fb_ad[12]  PORTC_PCR4=PORT_PCR_MUX(5);          //fb_ad[11]  PORTC_PCR5=PORT_PCR_MUX(5);          //fb_ad[10]  PORTC_PCR6=PORT_PCR_MUX(5);          //fb_ad[9]  PORTC_PCR7=PORT_PCR_MUX(5);          //fb_ad[8]  PORTC_PCR8=PORT_PCR_MUX(5);          //fb_ad[7]  PORTC_PCR9=PORT_PCR_MUX(5);          //fb_ad[6]  PORTC_PCR10=PORT_PCR_MUX(5);         //fb_ad[5]    PORTC_PCR12=PORT_PCR_MUX(5);          //fb_d[11]  PORTC_PCR13=PORT_PCR_MUX(5);          //fb_d[10]  PORTC_PCR14=PORT_PCR_MUX(5);          //fb_d[9]  PORTC_PCR15=PORT_PCR_MUX(5);          //fb_d[8]    PORTD_PCR2=PORT_PCR_MUX(5);          //fb_a[4]  PORTD_PCR3=PORT_PCR_MUX(5);          //fb_a[3]  PORTD_PCR4=PORT_PCR_MUX(5);          //fb_a[2]  PORTD_PCR5=PORT_PCR_MUX(5);          //fb_a[1]  PORTD_PCR6=PORT_PCR_MUX(5);          //fb_a[0]    PORTD_PCR8=PORT_PCR_MUX(6);          //fb_a[16]  PORTD_PCR9=PORT_PCR_MUX(6);          //fb_a[17]  PORTD_PCR10=PORT_PCR_MUX(6);         //fb_a[18]  PORTD_PCR11=PORT_PCR_MUX(6);         //fb_a[19]  PORTD_PCR12=PORT_PCR_MUX(6);         //fb_a[20]  PORTD_PCR13=PORT_PCR_MUX(6);         //fb_a[21]  PORTD_PCR14=PORT_PCR_MUX(6);         //fb_a[22]  PORTD_PCR15=PORT_PCR_MUX(6);         //fb_a[23]  //control signals  PORTB_PCR19=PORT_PCR_MUX(5);          //fb_oe_b  PORTC_PCR11=PORT_PCR_MUX(5);          //fb_rw_b  PORTC_PCR16=PORT_PCR_MUX(5);          //FB_BE23_16  PORTC_PCR17=PORT_PCR_MUX(5);          //FB_BE31_24  PORTC_PCR18=PORT_PCR_MUX(5);          //fb_cs2_b

[scotty]

There is some demo code (flexbus.c), which accesses the MRAM on the TWR-MEM with a Freescale Tower System.

But Attention:

If you have Revision C of the TWR-K60N512 you have to unsolder C2 and R14.