FlexCAN Errata e2583 (K20F120)

[mjbcswitzerland]

Hi All

Early silicon (0M33Z) had a FlexCAN errata e2583 which requires the OSCERCLK source to be enabled in order for CAN to function properly.

Since I am presently working with CAN on a K20FX512VLQ12 (revision 3N96B) and this errata is no longer is reported the workaround was disabled. However then the problem starts exactly as described in e2583 - the CAN controller won't leave the low power state.

So the workaround has had to be left on.

Is this expected and has maybe the errata not been solved?

Regards

Mark

[Hui_Ma · Accepted solution]

Hi Mark,

First of all, thank you for the patience.

The errata e2583 had been fixed in silicon 3N96B.

It have to set the CAN_CTRL1[CLKSRC] bit before clearing CAN_MCR[MDIS]. Maybe that is why you think you are seeing an issue. By default the clock source is configured to use the oscillator (ERCLK), so if you clear MDIS with the default configuration (without setting CTRL1[CLKSRC]) then the LPMACK bit will set because the CAN module doesn’t have a valid clock. You have to configure it to use the bus clock first, then clear the MDIS bit, then LPMACK will clear as expected.

Wish it helps.

With regards,

Ma Hui

[mjbcswitzerland]

Hi Ma

Many thanks - I have been using the external clock source and not the bus clock source, which means that I HAVE TO enable it.

The confusion seems to come from the fact that the original code comes from the Coldfire FlexCAN project where the clock source could be selected but didn't have to be enabled too. This means that I now understand the original errata as "the external source has to be enabled in order to configure the CAN controller irrespective of whether the external or bus clock will be used".

If I were to use the bus clock I think that I would have had the problem that you describe since I was setting the source after moving to the freeze mode - I now also changed the code ordering so that the clock settings are written before moving to freeze mode in order to avoid this problem if I were to select the bus clock source in the furure.

The original simplified pseudo code was:

#IF ERRATE NEEDED // compile time decision

    enable external clock source

#ENDIF

move to freeze mode

configure the clock (speed and select clock source)

It is now:

IF EXTERNAL CLOCK SOURCE TO BE USED // run time decision

    enabled external clock source

ELSE

    do nothing

ENDIF

configure the clock (speed and select clock source)

move to freeze mode

Regards

Mark

[Hui_Ma]

Hi Mark,

I am checking with Kinetis 120/150MHz product engineer about K20FX512VLQ12 (revision 3N96B) FlexCAN module errata status.

The product engineer is on vacation, it need some time to wait for he back to office.

Thank you for the patience and understanding.

B.R.

Ma Hui