FTM0_CH6 (160 kHz) sync with FTM2_CH0 (16 kHz) on FRDM-K64F

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FTM0_CH6 (160 kHz) sync with FTM2_CH0 (16 kHz) on FRDM-K64F

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Rashmitha_Nair
Contributor III

Hi,

I am trying to debug an existing project.

I have a 160 kHz SPWM signal which uses DMA to update its samples and a 16 kHz clock signal.

The project uses a state machine for setting particular states and has a trigger button that starts SPWM generation. Each time the Trigger button is pressed to turn on and off the PWM outputs, I see that the SPWM samples shift by a certain number w.r.t to the rising edge of 16kHz signal. I would like to make the samples aligned with the rising edge and not shift on trigger on trigger off button presses.

Below is my Flex Timer Initialization and DMA initialization code. 

bool initializePWM(outputWaveShape shape, uint32_t fOutput, uint32_t fClock, uint32_t deadTime)
{
	uint32_t FTM0ModVal = 0;
	uint32_t dtVal = 0;

	switch(shape)
	{
	case sine:
		FTM0ModVal = 1 / ((1 / (float) fClock) / (1 / (2 * (float) fOutput * (float) BUFF_LENGTH)));
		break;
	case square:
		FTM0ModVal = 1 / ((1 / (float) fClock) / (1 / (2 * (float) fOutput)));
		break;
	}

	/**********************************************************************************
	 * PORT SETUP
	 * ********************************************************************************
	 */

	// System Clock Gating Control Register 5 (SIM_SCGC5), switch on clock for port A
	*(volatile unsigned long *)(SIM_BLOCK + SIM_PORT_CLK_GATE_OFFSET) |= 0x00000200;

    // FTM0_CH6 on PTA1 (alt. function 3) and high drive strength
    *(volatile unsigned long *)(PORTA_BLOCK + 0x04) |= (0x00000300 | 0x00000040);

    // FTM0_CH7 on PTA2 (alt. function 3)
     *(volatile unsigned long *)(PORTA_BLOCK + 0x08) |= (0x00000300 | 0x00000040);

 	/**********************************************************************************
 	 * Timer Channel n Setup
 	 * ********************************************************************************
 	 */

 	// FTM. Ensure that the FlexTimer/TPM module is powered up
     *(volatile unsigned long *)(SIM_BLOCK + 0x103c) |= 0x01000000;

    // FTM Status And Control (FTM0_SC). Disable FTM0 operation (system clock)
    *(volatile unsigned long *)(FTM0_BASE_ADDR + 0x000) = 0x00000000;

    /* Configuration (FTMx_CONF) pp 1020
     * pin
     * 6 - 7 - BDM mode 3 - 0xc0 (allow timer to continue operating when debugging). BDM mode 1 - 0x40
     *  --------------------------------------------------------------------------------------------------------------------------
     * |BDMMODE | FTM Counter | CH(n)F Bit   | FTM Channels                    | Output Writes to MOD, CNTIN, and C(n)V Registers |
     * |--------|-------------|--------------|---------------------------------|--------------------------------------------------|
     * |00      | Stopped     |  can be set  |                                 | Writes to these registers bypass the registers   |
     * |        |             |              |                                 | buffers                                          |
     * |--------|-------------|--------------|---------------------------------|--------------------------------------------------|
     * |01      | Stopped     |  is not set  | The channels outputs are forced | Writes to these registers bypass the registers   |
     * |(0x40)  |             |              | to their safe value according   |                                                  |
     * |        |             |              | to POLn bit buffers             |                                                  |
     * |--------|-------------|--------------|---------------------------------|--------------------------------------------------|
     * |10      | Stopped     |  is not set  | The channels outputs are forced | Writes to these registers bypass the registers   |
     * |        |             |              | to their safe value according   |                                                  |
     * |        |             |              | to POLn bit buffers             |                                                  |
     * |--------|-------------|--------------|---------------------------------|--------------------------------------------------|
     * |11      | Functional  |  can be set  | functional mode                 | functional mode                                  |
     * |(0xc0)  | mode        |              |                                 |                                                  |
     * |        |             |              |                                 |                                                  |
     *  --------------------------------------------------------------------------------------------------------------------------
     *
     * 9     - Enable use of global timebase from another FTM module 0x200 - not here this is the module that will act as master
     * 10 	 - Enable output of global timebase to other FTMs 0x400 - not yet though. use this to start FTM0 and FTM1 synchronously
     *
     * For debugging the Flextimer without driving it from the DMA, 0x40 is useful. For debugging the control loop 0xc0 is better
     * because it allows the switching to keep going even if the control loop is being interrogated.
     */
    //*(unsigned long *)(FTM0_BASE_ADDR + 0x084) |= (0x00000040);
    *(unsigned long *)(FTM0_BASE_ADDR + 0x084) = (0x000000c0);

    // Disable Write protection on the FTMx_MODE.
    *(unsigned long *)(FTM0_BASE_ADDR + 0x054) = 0x00000004;

    // Features Mode Selection (FTMx_MODE)
    // Switch on the enhanced FTM features - 0x01
    // Keep write protection disabled - 0x04
    *(unsigned long *)(FTM0_BASE_ADDR + 0x054) = (0x00000004 | 0x00000001);

    // Synchronisation (FTMx_SYNC).
    // Enable loading at maximum (i.e. CV == MOD) - 0x00000002
    // Software triggering is enabled - 0x80
    *(unsigned long *)(FTM0_BASE_ADDR + 0x58) = (0x00000002 | 0x80);

    // Set counter MOD register to the value that provides the frequency of interest.
    // 0xBB0; - 20 kHz
    // 0x6B2; - 35 kHz
    // 0x3C8; - 62 kHz
    // 0x0BB; - 320 kHz
    *(volatile unsigned long *)(FTM0_BASE_ADDR + FTM0_MOD) =  (FTM0ModVal - 1);

    // A counter
    int i = 0;

    // Pointer to the address of the FTM Modulo register.
	volatile unsigned long *mod;
	mod = (unsigned long *)(FTM0_BASE_ADDR + FTM0_MOD);

	// write the data that will be passed by the DMA to the FTM CnV registers.
	for(i = 0 ; i<BUFF_LENGTH; i++)
	{
		PWMAData[i] = 0;

		switch(shape)
		{
		case sine:
			// prevent large voltage output when timer starts...
			s->tempmaxDutyPercent = 0;
			ModulatedSineDutyValues[i] = (( (int16_t) dutyCyclePercentSine[i] - 50) * s->tempmaxDutyPercent)/100 + 50;
			PWMBData[i] = (*mod * (ModulatedSineDutyValues[i]) / 100) + PWMAData[i];
			break;

		case square:
			PWMBData[i] = (*mod * (dutyCyclePercentSquare[i]) / 100) + PWMAData[i];
			break;
		}

		/* Synchronisation (FTMx_SYNC) register DMA memory buffer.
		 * 0x80 is the software sync flag. The hardware clears this after every sync.
		 * 0x02 is the flag that sets the synchronisation of registers with buffers to happen when CV == MOD.
		 * this only happens if the software sync flag has been raised prior to CV == MOD occurring.
		 * 0x08 is the output mask enable bit.
		 */
		SyncData[i] = (0x80 | 0x02 | 0x08);
	}

    /* Synchronisation Configuration (FTMx_SYNCONF)
     * set SYNCMODE (Enhanced PWM synchronisation is selected.) - 0x80
     * set SWRSTCNT = 1 (FTM counter synchronisation is activated by the software trigger) - 0x100
     * set SWWRBUF = 1 (MOD, CNTIN, and CV registers synchronisation is activated by the software trigger.) - 0x200
	 * set SWOM = 1 (Software Output Mask register is updated from its buffer by the software trigger) - 0x400
	 */
    *(unsigned long *)(FTM0_BASE_ADDR + 0x8C) = (0x200 | 0x80 |0x400);

    // Channel (n) Status And Control (FTMx_CnSC)
    // DMA = 1 - 0x01
    // ELSnB:ELSnA = 1:0 Edge-Aligned PWM High-true pulses (clear Output on match) - 0x08
    // MSnB:MSnA = 1:0 (See ELSnB:ELSnA) - 0x20
    // CHIE = 1 Enable Channel interrupts (necessary for DMA to be fired but when DMA = 1 the interrupt itself is not generated) - 0x40
    *(volatile unsigned long *)(FTM0_BASE_ADDR + FTM0_C6SC_OFFSET) = (0x00000020 | 0x00000008 | 0x00000001 | 0x00000040);

    // Set counter initial value to zero
    *(volatile unsigned long *)(FTM0_BASE_ADDR + 0x04c) = 0;

    // prepare first PWM value (place it in the CnV register)
    *(volatile unsigned long *)(FTM0_BASE_ADDR + FTM0_C6V_OFFSET) = *ptrPWMABuffer;

    // prepare output mask for running the inverter
    *(volatile unsigned long *)(FTM0_BASE_ADDR + 0x60) = (0xC0);


	/**********************************************************************************
 	 * Timer Channel n+1 Setup
 	 * ********************************************************************************
 	 */

    // Channel (n) Status And Control (FTMx_CnSC)
    // DMA = 1 - 0x01
    // ELSnB:ELSnA = 1:0 Edge-Aligned PWM High-true pulses (clear Output on match) - 0x08
    // MSnB:MSnA = 1:0 (See ELSnB:ELSnA) - 0x20
    // CHIE = 1 Enable Channel interrupts (necessary for DMA to be fired but when DMA = 1 the interrupt itself is not generated) - 0x40
    *(volatile unsigned long *)(FTM0_BASE_ADDR + FTM0_C7SC_OFFSET) = (0x00000020 | 0x00000008 | 0x00000001 | 0x00000040);

    // Function For Linked Channels (FTMx_COMBINE).
    // Enable combined mode on CH6 and CH7 bit 24 - 0x1000000
    // Enable complimentary mode on CH6 and CH7 bit 25 - 0x2000000
    // Enable Deadtime on CH6 and CH7 bit 28 - 0x10000000
    // Enable PWM Synchronisation between CH6 and CH7 bit 29 - 0x20000000
    *(unsigned long *)(FTM0_BASE_ADDR + 0x64) = (0x1000000 | 0x2000000 | 0x20000000);

    // Deadtime Insertion Control (FTMx_DEADTIME) 80 is pre-scaler of 4 0x3C is 60
    //(0x1E | 0x80) - 2us
    // 0x3C - 1us
    // The bus clock used for this which is (system clock / 2) (60MHz in the FRDM case). The final value is in clock ticks, deadTime is in ns.
    // if no prescaler is required then the deadtime is calculated using the first 6 bits of the dead time register.
    // If a value more than 0x40 * the divided system clock is needed then the pre-scaler must be used.
    // Bits 6 and 7 are responsible for a prescaler of:
    // 6,7
    // 0x - 1
    // 10 - 4
    // 11 - 16

	dtVal = (uint32_t)(deadTime *  ( (float) fClock / 10e6) / 200 );

    if (dtVal > 0x3F)
    {
    	// The deadtime is more than the maximum without a pre-scaler
    	if ((dtVal / 4) < 0x40 )
    	{
    		// The deadtime is less than the maximum with a pre-scaler of 4 so set the pre-scaler to 4
    		*(volatile unsigned long *)(FTM0_BASE_ADDR + 0x68) |= 0x80;
    		dtVal = dtVal / 4;
    		*(volatile unsigned long *)(FTM0_BASE_ADDR + 0x68) |= dtVal;
    	}
    	else
    	{
   			if((dtVal / 16) < 0x40)
   			{
   				// The dead-time is less than the maximum with a prescaler of 16 so set the pre-scaler to 16.
   				*(volatile unsigned long *)(FTM0_BASE_ADDR + 0x68) |= 0xC0;
   				dtVal = dtVal / 16;
   				*(volatile unsigned long *)(FTM0_BASE_ADDR + 0x68) |= dtVal;
   			}
   			else
   			{
    			// The dead-time is more than the maximum value even with a pre-scaler of 16, or something else is wrong.
    			// return an error.
    			return true;
   			}
    	}
    }
    else
    {
    	*(volatile unsigned long *)(FTM0_BASE_ADDR + 0x68) |= dtVal;
    }

    // prepare first PWM value (place it in the CnV register)
    *(volatile unsigned long *)(FTM0_BASE_ADDR + FTM0_C7V_OFFSET) = *ptrPWMBBuffer;
    return false;
}

 

void initializeDMA()
{

	/**********************************************************************************
 	 * Channel n DMA Setup
 	 * ********************************************************************************
 	 */

    // eDMA TCD Signed Source Address Offset (DMA_TCD1_SOFF) i.e. source address increment per DMA minor loop
    *(signed short *)(eDMA_DESCRIPTORS + 0x024) = sizeof(unsigned short);

    // eDMA TCD Signed Destination Address Offset (DMA_TCD1_DOFF) i.e. destination address is not incremented
    *(signed short *)(eDMA_DESCRIPTORS + 0x034) = 0;

    // eDMA TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD1_DLASTSGA). No destination displacement on transmit buffer completion
    *(volatile signed long *)(eDMA_DESCRIPTORS + 0x038) = 0;

    // eDMA TCD Last Source Address Adjustment (DMA_TCD1_SLAST). When the buffer has been transmitted set the destination back to the start of the buffer.
    *(volatile unsigned long *)(eDMA_DESCRIPTORS + 0x02c) = (-(signed long)(sizeof(PWMAData)));

    // eDMA TCD Transfer Attributes (DMA_TCD1_ATTR). Transfer size is half-words i.e. 16 bits, the same as the destination register width.
    *(unsigned short *)(eDMA_DESCRIPTORS + 0x026) = (0x0001 | 0x0100);

    // eDMA TCD Source Address (DMA_TCD1_SADDR).
    *(volatile unsigned long *)(eDMA_DESCRIPTORS + 0x020) = (unsigned long)ptrPWMABuffer;

    // eDMA TCD Control and Status (DMA_TCD1_CSR). Free-running mode without any interrupt
    *(volatile unsigned short *)(eDMA_DESCRIPTORS + 0x03c) = 0;

    // eDMA TCD Destination Address (DMA_TCD1_DADDR). Destination address is the FTM CnV register (the PWM register)
    *(volatile unsigned long *)(eDMA_DESCRIPTORS + 0x030) = (unsigned long)((FTM0_BASE_ADDR + FTM0_C6V_OFFSET));

    // eDMA TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD1_NBYTES_MLNO). Each request starts a single transfer of this size (minor byte transfer count)
    *(volatile unsigned long *)(eDMA_DESCRIPTORS + 0x028) = sizeof(unsigned short);

    // eDMA TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD1_BITER_ELINKNO).
    // The number of service requests to be performed each buffer cycle.
    *(unsigned short *)(eDMA_DESCRIPTORS + 0x03e) = *(volatile signed short *)(eDMA_DESCRIPTORS + 0x036) = (signed short)(sizeof(PWMAData) / sizeof(unsigned short));


 	/**********************************************************************************
 	 * Channel n+1 DMA Setup
 	 * ********************************************************************************
 	 */

    // eDMA TCD Signed Source Address Offset (DMA_TCD2_SOFF) i.e. source address increment per DMA minor loop
    *(signed short *)(eDMA_DESCRIPTORS + 0x044) = sizeof(unsigned short);

    // eDMA TCD Signed Destination Address Offset (DMA_TCD2_DOFF) i.e. destination address is not incremented
    *(signed short *)(eDMA_DESCRIPTORS + 0x054) = 0;

    // eDMA TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD2_DLASTSGA). No destination displacement on transmit buffer completion
    *(volatile signed long *)(eDMA_DESCRIPTORS + 0x058) = 0;

    // eDMA TCD Last Source Address Adjustment (DMA_TCD2_SLAST). When the buffer has been transmitted set the destination back to the start of the buffer.
    *(volatile unsigned long *)(eDMA_DESCRIPTORS + 0x04c) = (-(signed long)(sizeof(PWMBData)));

    // eDMA TCD Transfer Attributes (DMA_TCD2_ATTR). Transfer size is half-words i.e. 16 bits, the same as the destination register width.
    *(unsigned short *)(eDMA_DESCRIPTORS + 0x046) = (0x0001 | 0x0100);

    // eDMA TCD Source Address (DMA_TCD2_SADDR).
    *(volatile unsigned long *)(eDMA_DESCRIPTORS + 0x040) = (unsigned long)ptrPWMBBuffer;

    // eDMA TCD Control and Status (DMA_TCD2_CSR). Free-running mode without any interrupt
    *(volatile unsigned short *)(eDMA_DESCRIPTORS + 0x05c) = 0;

    // eDMA TCD Destination Address (DMA_TCD2_DADDR). Destination address is the FTM CnV register (the PWM register)
    *(volatile unsigned long *)(eDMA_DESCRIPTORS + 0x050) = (unsigned long)((FTM0_BASE_ADDR + FTM0_C7V_OFFSET));

    // eDMA TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD2_NBYTES_MLNO). Each request starts a single transfer of this size (minor byte transfer count)
    *(volatile unsigned long *)(eDMA_DESCRIPTORS + 0x048) = sizeof(unsigned short);

    // eDMA TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD2_BITER_ELINKNO).
    // The number of service requests to be performed each buffer cycle.
    *(unsigned short *)(eDMA_DESCRIPTORS + 0x05e) = *(volatile signed short *)(eDMA_DESCRIPTORS + 0x056) = (signed short)(sizeof(PWMBData) / sizeof(unsigned short));


 	/**********************************************************************************
 	 * Sync Channel DMA Setup
 	 * ********************************************************************************
 	 */

    // eDMA TCD Signed Source Address Offset (DMA_TCD3_SOFF) i.e. source address increment per DMA minor loop
    *(signed short *)(eDMA_DESCRIPTORS + 0x064) = sizeof(uint8_t);

    // eDMA TCD Signed Destination Address Offset (DMA_TCD3_DOFF) i.e. destination address is not incremented
    *(signed short *)(eDMA_DESCRIPTORS + 0x074) = 0;

    // eDMA TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD3_DLASTSGA). No destination displacement on transmit buffer completion
    *(volatile signed long *)(eDMA_DESCRIPTORS + 0x078) = 0;

    // eDMA TCD Last Source Address Adjustment (DMA_TCD3_SLAST). When the buffer has been transmitted set the destination back to the start of the buffer.
    *(volatile unsigned long *)(eDMA_DESCRIPTORS + 0x06c) = (-(signed long)(sizeof(SyncData)));

    // eDMA TCD Transfer Attributes (DMA_TCD3_ATTR). Transfer size is bytes i.e. 8 bits, the same as the destination register width.
    *(unsigned short *)(eDMA_DESCRIPTORS + 0x066) = 0x000;

    // eDMA TCD Source Address (DMA_TCD3_SADDR).
    *(volatile unsigned long *)(eDMA_DESCRIPTORS + 0x060) = (unsigned long)ptrSYNCBuffer;

    // eDMA TCD Control and Status (DMA_TCD3_CSR). Free-running mode without any interrupt
    *(volatile unsigned short *)(eDMA_DESCRIPTORS + 0x07c) = 0;

    // eDMA TCD Destination Address (DMA_TCD3_DADDR). Destination address is the FTM Sync register
    *(volatile unsigned long *)(eDMA_DESCRIPTORS + 0x070) = (unsigned long)((FTM0_BASE_ADDR + 0x58));

    // eDMA TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCD3_NBYTES_MLNO). Each request starts a single transfer of this size (minor byte transfer count)
    *(volatile unsigned long *)(eDMA_DESCRIPTORS + 0x068) = sizeof(uint8_t);

    // eDMA TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD3_BITER_ELINKNO).
    // The number of service requests to be performed each buffer cycle.
    *(unsigned short *)(eDMA_DESCRIPTORS + 0x07e) = *(volatile signed short *)(eDMA_DESCRIPTORS + 0x076) = (signed short)(sizeof(SyncData) / sizeof(uint8_t));


 	/**********************************************************************************
 	 * Channel n DMA Multiplexer Setup
 	 * ********************************************************************************
 	 */

    // System Clock Gating Control Register 6 (SIM_SCGC6). Enable DMA Multiplexer.
     *(volatile unsigned long *)(SIM_BLOCK + 0x103c) |= 0x00000002;

    // Channel Configuration register (DMAMUX_CHCFG1). Connect trigger source to DMA channel 1.
     *(unsigned char *)(DMAMUX0_BLOCK + 0x01) = (unsigned char)(DMAMUX_SOURCE_SLOT_FTM0_CH6 | 0x80);


 	/**********************************************************************************
 	 * Channel n+1 DMA Multiplexer Setup
 	 * ********************************************************************************
 	 */

    // Channel Configuration register (DMAMUX_CHCFG2). Connect trigger source to DMA channel 2.
     *(unsigned char *)(DMAMUX0_BLOCK + 0x02) = (unsigned char)(DMAMUX_SOURCE_SLOT_FTM0_CH7 | 0x80);


  	/**********************************************************************************
  	 * Sync Channel DMA Multiplexer Setup
  	 * ********************************************************************************
  	 */

     // Channel Configuration register (DMAMUX_CHCFG2). Connect trigger source to DMA channel 3.
     *(unsigned char *)(DMAMUX0_BLOCK + 0x03) = (unsigned char)(DMAMUX_SOURCE_SLOT_FTM0_CH6 | 0x80);



 	/**********************************************************************************
 	 * Enable DMA Channels
 	 * ********************************************************************************
 	 */

    // eDMA Enable Request Register (DMA_ERQ). Enable the DMA channel 1 operation for FTM channel n
     *(volatile unsigned long *)(eDMA_BASE_ADDR + 0x00c) |= 0x00000002;

    // eDMA Enable Request Register (DMA_ERQ). Enable the DMA channel 2 operation for FTM channel n + 1
     *(volatile unsigned long *)(eDMA_BASE_ADDR + 0x00c) |= 0x00000004;

     // eDMA Enable Request Register (DMA_ERQ). Enable the DMA channel 3 operation for FTM channel Sync
     *(volatile unsigned long *)(eDMA_BASE_ADDR + 0x00c) |= 0x00000008;

}

Regards,

Rashmitha

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Rashmitha_Nair
Contributor III

Hi @CarlosGarabito ,

Thanks for your reply.

My issue was not due to the PWM setup itself, it was due to another function having a blocking while loop which was interfering with synchronization timings.

The problem appears to be solved for now, thank you again for taking the time to look into this!

 

Regards,

Rashmitha

 

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CarlosGarabito
NXP Employee
NXP Employee

Hi @Rashmitha_Nair , Thank you so much for your patience, I really appreciate it.

Regarding your issue, we are working on it to give you a proper answer to that one. Have you tried already to use the same FTM module? For example FTM0_CH0 and FTM0_CH1 to syncronise them?

 

As far as we know, you can syncronise the PWM signals only if you use the same FTM module.

 

Did you check some application notes in this area (Kinetis FTM) are AN4410, AN4381, AN4560 and AN5142?

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Rashmitha_Nair
Contributor III

Hi @CarlosGarabito ,

Thank you for your response.

I see that, in the code that I provided above, if I change the below line

*(unsigned long *)(FTM0_BASE_ADDR + 0x084) = (0x000000c0);

to

*(unsigned long *)(FTM0_BASE_ADDR + 0x084) = (0x000002c0);

 

Then FTM0_CH6 and FTM2_CH0 are synchronized, which is very strange because FTM0 is acting as the global timebase and this particular value change indicates that FTM0 is to follow the global timebase, as per my understanding.

However, althought the synchronization happens what I see is that the sync happens from the last DMA samples. So I moved my first value to the last position in DMA samples array to get a proper sine PWM.

What I am ultimately trying to achieve is on this post Sync between multiple FRDM K64F boards for PWM gen... - NXP Community where these 160kHz and 16kHz are the signals from Master to Slaves. The 160kHz SPWM is given to FTM0_FLT0 pin on slave (which resets the FTM0 counter) and the 16kHz is given to a GPIO pin which re-initiates the DMA. This is not successful though because of the timing issues induced by the presence of a state machine.

I would like to generate complementary SPWMs on FTM0 CH6 & CH7 on all slaves synchronized.

 

Thanks,

Rashmitha

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CarlosGarabito
NXP Employee
NXP Employee

Hi @Rashmitha_Nair Hi, on the application note AN5142  ( https://www.nxp.com/docs/en/application-note/AN5142.pdf ) on chapter 3.14 you can find what you are looking for, check it.

You can also see this Community thread which can help you because the man in the thread makes something like you want https://community.nxp.com/t5/Kinetis-Microcontrollers/FRDM-K64F-FTM-DMA-for-SPWM-Generation-in-compl...

 

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Rashmitha_Nair
Contributor III

Hi @CarlosGarabito ,

Thanks for your reply.

My issue was not due to the PWM setup itself, it was due to another function having a blocking while loop which was interfering with synchronization timings.

The problem appears to be solved for now, thank you again for taking the time to look into this!

 

Regards,

Rashmitha

 

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Rashmitha_Nair
Contributor III

Hi @CarlosGarabito ,

My code seems to be working fine when operating with low voltages but when I use higher voltage there seems to be some noise interference that causes the sync to fail and shuts down PWM output on slave modules.

 

Could you suggest any PWM synchronization scheme that has proven to be immune in high voltage environments? or any other suggestions you might have?

 

Regards,

Rashmitha

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CarlosGarabito
NXP Employee
NXP Employee

Could you explain it more clearly?. the board work with 0v for a logic 0 and 3.3v for a logic 1, so, what are you doing? and how are you doing?, please

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Rashmitha_Nair
Contributor III

Hi @CarlosGarabito 

I am using the board for controlling power electronics circuits that generate high power. The noise/interference from these circuits are causing the synchronization between the boards to fail.

The same code when used away from these power electronics boards, works well.

So is there any synchronization scheme that might be immune in such high power environments?

 

Regards,

Rashmitha

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CarlosGarabito
NXP Employee
NXP Employee

Hi @Rashmitha_Nair , but this case is different to the original tread, so i suggest to open a new issue, but, from now on I tell you (I'm almost certain) that your fault could be in the electronic circuits that you are connecting to the GPIOs of the board

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