FTM generate pulse, Unable to modify CnV register

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FTM generate pulse, Unable to modify CnV register

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Senior Contributor II

Hello

I'm on a K60 and test to generate pulse to drive stepper motor.

I have a working code which can generate a pulse of a determined wide and period. (CNTIN; MOD  / CnV; C(n+1)V)

Then with the following code I generate a square signal (CNTIN = 0, MOD = 65535, Cnv = 1, Cn+1V = 0x8000)

SIM->SCGC6 |= SIM_SCGC6_FTM0_MASK; FTM0->MODE = FTM_MODE_WPDIS_MASK | FTM_MODE_INIT_MASK ;  /* Set up mode register */ FTM0->MODE |= FTM_MODE_FTMEN_MASK;  /* FTMEN bit is write protected. Can be written only when WPDIS = 1 */ FTM0->SC = (uint32_t)0x00UL;  /* Clear status and control register */ FTM0->CNTIN= (uint32_t)0x00UL;  /* Clear counter initial register */ FTM0->MOD = (uint32_t)(DV_PWM_MODULO-1);  /* Set up modulo register */ FTM0->CNT = (uint32_t)0x00UL;  /* Reset counter register */ FTM0->CONTROLS[0].CnSC = FTM_CnSC_ELSB_MASK;  FTM0->CONTROLS[1].CnSC = FTM_CnSC_CHIE_MASK;  FTM0->COMBINE = FTM_COMBINE_COMBINE0_MASK;  FTM0->CONTROLS[0].CnV= 1/* Allow to modify pulse start */ FTM0->CONTROLS[1].CnV = 0x8000/* Allow to modify Pulse end */   PORTC->PCR[1]= PORT_PCR_MUX(4); FTM0->SC= (uint32_t)(/* //debug AG FTM_SC_TOIE_MASK |*/ FTM_SC_CLKS(1) | FTM_SC_PS(DV_PWM_PRESCALER));  /* Set up status and control register */

To test some possibility, I just configure the CHn+1IE and Flag to generate the interrupt on Falling edge (Cn+1V = FTM Counter)

void __attribute__ ((interrupt)) DV_Pwm_FTM0IRQ(void) { /* Toggle port debug */ PTC->PTOR |= 0x00000001; /* Increment Cn+1V */ FTM0->CONTROLS[1].CnV++; FTM0->CONTROLS[1].CnSC &= ~FTM_CnSC_CHF_MASK; // clear flag }

But after test, IT occurs because My debug Pin on PTC0  toggle.

But the Cn+1V which is incremented on the Interrupt has no effect on my output signal which should pass from a initial duty cycle of 50% to 100% and then 0%  to 100% etc...

But signal still 50% duty!.

SYNCEN is set to 0,

so I don't see why Cn+1V is not impacted?

Smiley Happy

I read the RM, But I think the Update register should be OK because SYNCEN = 0 & SYNCMODE = 0):

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1 Solution
86 Views
NXP Employee
NXP Employee

Hi Arno,

I think you will find that if you FTMEN = 1, you must load the CnV registers according to the PWM Synchronization rules.  Meaning that you will need to set the SYNCEN bit in the Combine register and then setup the synchronization according to how you want to synchronize the registers.  Here is a snippet of code that will set up your FTM for software synchronization:

FTM0_COMBINE |= FTM_COMBINE_SYNCEN0_MASK;

        FTM0_SYNCONF |= (FTM_SYNCONF_SWWRBUF_MASK |

                        FTM_SYNCONF_SWRSTCNT_MASK |

                        FTM_SYNCONF_SYNCMODE_MASK

                        );

This should be inserted in your setup code.  Once you have this configuration, remember to add a write to the SWSYNC bit after writing your CnV register in your interrupt routine. This write triggers the load of the CnV registers so that they take effect. 

FTM0_SYNC |= FTM_SYNC_SWSYNC_MASK;

There are other ways to control how the registers are loaded when you have FTMEN = 1, but I think this is the simplest fastest method for you at this point.  Please let me know if you are interested in other ways or if you have any other questions about this method. 

Regards,

Chris

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Senior Contributor II

Ok

In fact I remove the FTM counter syncrhonisation:

FTM0->SYNCONF |= (FTM_SYNCONF_SWWRBUF_MASK |  //FTM_SYNCONF_SWRSTCNT_MASK |    FTM_SYNCONF_SYNCMODE_MASK  ); 

Ann add following config:

FTM0->SYNC |= FTM_SYNC_CNTMIN_MASK;

Smiley Happy

86 Views
Senior Contributor II

Hi,

I have another problem.

By the way explain above, CnV anc Cn+1V (Refresh in Cn+1V IT) are updated on the FTM counter pass from High value (0xFFFF) to low value (0x0000)

But in my case, I want in the Cn+1V refresh CnV and Cn+1V and taken immediately in the same FTM cycle, Not wait end of Counter reach max value (MOD), but immediately and then if new CnV / Cn+1V match TMR counter value, modify output and then generate interrupt..

Is there possible with the FTM?

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Senior Contributor II

In simple word,

are they a means to update CnV and Cn1V in the CHnIE interrupt (or CHn+1IE) and the new value was taken immediately, without wait next synchronisation on FTM overflow?

87 Views
NXP Employee
NXP Employee

Hi Arno,

I think you will find that if you FTMEN = 1, you must load the CnV registers according to the PWM Synchronization rules.  Meaning that you will need to set the SYNCEN bit in the Combine register and then setup the synchronization according to how you want to synchronize the registers.  Here is a snippet of code that will set up your FTM for software synchronization:

FTM0_COMBINE |= FTM_COMBINE_SYNCEN0_MASK;

        FTM0_SYNCONF |= (FTM_SYNCONF_SWWRBUF_MASK |

                        FTM_SYNCONF_SWRSTCNT_MASK |

                        FTM_SYNCONF_SYNCMODE_MASK

                        );

This should be inserted in your setup code.  Once you have this configuration, remember to add a write to the SWSYNC bit after writing your CnV register in your interrupt routine. This write triggers the load of the CnV registers so that they take effect. 

FTM0_SYNC |= FTM_SYNC_SWSYNC_MASK;

There are other ways to control how the registers are loaded when you have FTMEN = 1, but I think this is the simplest fastest method for you at this point.  Please let me know if you are interested in other ways or if you have any other questions about this method. 

Regards,

Chris

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86 Views
Senior Contributor II

Hello

Thank for your help, I will test this.

I must first make sure this solution does not add jitter on Pwm counter.

In other word, the fact to modify CnV or Cn+1V must not modify other think like FTM counter an then delayed the signal.

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Senior Contributor II

After test, it seem not only the modified Cn+1V value is set but also MOD or something else!

The end signal is not that I expected!

With my code, without activate the Interrupt, When I change Cn+1V in a range between 2 to 65535, the signal keep always the same period (determined by CNTIN and MOD) and the the duty cycle evaluate from 0% to 100% according set value in Cn+1V.

Then I activate the Interrupt in which I make: Cn+1V = Cn+1V  + 1

Without your modifications above Cn+1V not change, signal still signal configured in init phase.

With your modifications, Duty cycle is always about 99.99999% (Always a fast low state) and the period change between "0" (or very small) to my configured period (50MHz / Prescaler (=1) / (MOD-CNTIN)) #1.3ms.. and the restart to 0 etc...

:smileysilly:

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NXP TechSupport
NXP TechSupport

Hi Arno Gir,

I'm still not very clear with phenomenon after you modify the Cn+1.

So I was wondering if you can explain it again and share your text code, then I reproduce this phenomenon on my board.
Have a great day,
Ping

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Senior Contributor II

In fact it seems FTM counter is reset when Cn+1V is loaded with  new value.

???

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NXP TechSupport
NXP TechSupport

Hi Arno Gir,

I think Chris show you the terrific way to update the CnV correctly and please refer to it.

If you have any further question, please just feel free to post.
Have a great day,
Ping

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