FRDM-KW40Z SPI Port to Shield Connector Errata

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FRDM-KW40Z SPI Port to Shield Connector Errata

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Contributor IV

Hello, Like to report some errata on the FRDM-KW40Z found by one of our customers. The blue text on the nets SW3 and SW4 that connects to the J1 shield connector on page 5 is wrong. Resulting in the SPI1 port clock and chip select lines being swapped on a custom board they built to mate to the Freedom board.

Net SW4, J1-10 on sheet 5 labled as PTA19/TSIO_CH13/SPI1_PCS0 but connects to PTA18 on the KW40

Net SW3, J1-12 on sheet 5 labled as  PTA18/TSIO_CH12/SPI1_SCK but connects to PTA19 on the KW40

I believe the problem is that the text in red is what the schematic capture tool uses to connect the nets. And the text in blue is supposed to be helpful “comments” and is wrong in this case. How is errata like this is documented on development boards? Maybe this is the first reported errata. Is there an errata document that is created and put under the "Documentation" tab?

Schematics for the FRDM-KW40Z are here:

FRDM-KW40Z|Freedom Development Platform|Kinetis MCU|NXP

Thanks!

Mark

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miduo
NXP Employee
NXP Employee

Hi,

I double checked the issue you mentioned, you are correct that we had the error for the two signal's connector. We are sorry that we do not have an official document errata at present. Anyway, I will report this issue to our document team and it will been addressed with some record. Thanks for reporeted the issue to us.

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