I check the ARM Cortex-M0 technical reference manual, there are two ways to execute the multiple operation.
The MULS instruction provides a 32-bit x 32-bit multiply that yields the least-significant 32-bits. The processor can implement MULS in one of two ways:
One way is as a fast single-cycle array, the other way as a 32-cycle iterative multiplier.
As my understanding the fast single-cycle array is to look up Multiplication table to get the result, which only need one cycle. The other way is just for typical multiple operation, will take 32 cycles.
That's why the actual multiple operation cycle number depends on multiplier implementation.
About Multiplication table size, it need to check with ARM.
Wish it helps.
