FRDM-K64: Anyway to control the SPI PCSn line as a gpio output?

cancel
Showing results for 
Search instead for 
Did you mean: 

FRDM-K64: Anyway to control the SPI PCSn line as a gpio output?

Jump to solution
540 Views
benhouston
Contributor III


I am trying to hold the assertion of the chip select line between byte transfers to a device. 

Example: Assert CSn->Send byte->CSn stays asserted->Send next byte....and so on until byte by byte transfer is complete.

On the FRDM-KL27, I can configure the CSn as a gpio.  I can then control the CSn as needed in firmware.

Not so on the K64.  Or is it???? 

Before you say...just make CSn continuous over transfers by using the CONT bit, I have to warn you.  According to SDK 2.0, I can only set this bit if my CPHA is equal to 1, which it is not.  Setting it to 1 would violate the slave devices specs.

I am using SDK 2.0 with IAR EWARM.

So...what would you do K64 ninjas?

0 Kudos
1 Solution
274 Views
egoodii
Senior Contributor III

The 'K' series has a whole signal-mux-control block for GPIO and peripheral signals.  Refer to that chapter in the RM for how to set the 'ALT' selection to set a pin 'back' to GPIO if the driver has 'assumed' it for SPI.

View solution in original post

0 Kudos
5 Replies
274 Views
jeremyzhou
NXP TechSupport
NXP TechSupport

Hi Ben,

I was wondering if you can clarify the question, I'm still confused with it after had a look through the statement.
Have a great day,
Ping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos
274 Views
benhouston
Contributor III

KL27 has the SPIx_C1[SSOE]  bit field to configure the CSn line as a gpio.  I don't see that in the K64 data sheet. 

0 Kudos
275 Views
egoodii
Senior Contributor III

The 'K' series has a whole signal-mux-control block for GPIO and peripheral signals.  Refer to that chapter in the RM for how to set the 'ALT' selection to set a pin 'back' to GPIO if the driver has 'assumed' it for SPI.

0 Kudos
274 Views
benhouston
Contributor III

When setting up registers on the slave device, I must send multiple bytes.  The n byte is written to the n register, sequentially.

In order to do this sequential register write access, I must hold the chip select line low (or continually assert it) between each byte transfer.  It should never go high, until all of the bytes have been sent out from the K64 master.

The slave device requires that data be captured on the leading edge of the SCK signal. Thus, SPIx_CTARn[CPHA] is 0 and incompatable with implementing SPIx_CTARn[CONT]. 

With that said, I need to control the chip select line as a GPIO or manually.  I cannot have the SPI module in hardware control it.

This is fairly easy to do for the KL27 in fsl_spi.h, however, not so clear in fsl_dspi.h for the K64. 

0 Kudos
274 Views
jeremyzhou
NXP TechSupport
NXP TechSupport

Hi Ben,

As the EARL GOODRICH mentioned, you can use configure the PROTx_PRCn[MUX] to configure the pin as the GPIO instead of the SPIx_PCSn.

Hope it helps.
Have a great day,
Ping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos