EzPort entrance debug sequence:
-You need to connect following pins: CS->EzPORT_CS_b; MISO->EZP_DO;MOSI->EZP_DI;SCK->EZP_CLK;GND->GND;GPIO->RESET(!!!same reset as in SWD);
-SPI settings: As it mentioned in the RefMan CPOL=0, CPHA=0 or CPOL=1, CPHA=1 it does mean that it wil work only with CPOL=0, CPHA=0 or if CPU will not answer change it to CPOL=1, CPHA=1(in my case 0-0 was not the case and it worked out only with 1-1, watch attached file)
(code example: SPI1_C1|=SPI_C1_SPE(1)|SPI_C1_MSTR(1)|SPI_C1_SPIE(1)|SPI_C1_CPHA(0)|SPI_C1_CPOL(0); for 0-0 or SPI1_C1|=SPI_C1_SPE(1)|SPI_C1_MSTR(1)|SPI_C1_SPIE(1)|SPI_C1_CPHA(1)|SPI_C1_CPOL(1); for 1-1
-Ezport entrance sequence is the following: CS_LOW->RESET_LOW->wait few uS->REST_HIGH->wait few uS->CS_HIGH
To check whether you succeed you have to send "write enable" command(0x06) followed by "read status register"(0x05). Watch attached file. If not answer->change polarity of SPI. If not answer again->check connection and FOPT register of target CPU(EzPort could be disabled but by default from manufaturer it is enabled)
Check attached file.