External SRAM on K20 Flexbus with MQX

[primozrebec]

Hi all,

we have a 1 MB of external SRAM organized as 512K * 16 bit that is connected to K20 MCU flexbus. Read from SRAM is always 16 bit (both bytes) but we DO NOT have FB_AD0 pin connected to SRAM address line 0. So only even addresses should be accessed.

We want to have another MQX memory pool in order to store larger amount of data (various data structures). I've sccessfuly created new memory pool and allocated space from it, just as it is described here: https://community.freescale.com/message/329322#329322

We are having an issue with byte access to external SRAM e.g. when writing values to byte array. In this case, writing to odd addresses overwrites values in even addresses. Writing word and integer values aren't problematic. How should i employ aligned SRAM access? Is there a way to modify linker script (we are using GCC)?

Best,

Primoz

[drqubit]

Hello Primoz Rebec.

I think is not an alingment problem. In 32 bit environment, your pointers shall be aligned.

I think your problem is with pointer arithmetics. If you have a byte array located at 0x60000000 by example and access array[1] or array+1, your address will be truncated cause your missing FB_AD0. If you use memcpy, accessing even pointers, your data should be copied right. By definition, if you access odd addresses in a word aligned memory, your access will fail. You can check it trying to write to an odd address in pflash.

If you need to write to an odd byte only, you shall implement a custom access driver. Read 2 bytes from prior even address, modify 1 byte and write word back again.

Regads

[primozrebec]

Hello Ivan,

thank you for you input on this. In fact, i already have a custom external SRAM access driver to read/write 16-bit data. But now i want to make this functionality transparent for the application SW developer. We have a complex SW architecture, which uses many data structures. Memory for structure instances is all dynamically allocated. Pointers to those structures are passed to lower layers (including low-level drivers). With this design it is now impossible to control memory addresses which are accessed and we don't want to do complete rework. Is there a way to resolve this issue?

Best,

Primoz

[drqubit]

I fear you can directly access any odd address without FB_AD0. If your external SRAM don't have byte address, you can solve it using an intermediate cache memory.

Best regards.

[primozrebec]

OK, i managed to:

- change a linker file, i added external SRAM region to linker file

- change my application, i defined a static byte array this memry region using "__attribute__ ... " keyword

I am able to access this array but i still have problems writing byte values to it, because writing to odd addresses re-write complete word value in external SRAM.

I dont see any possibility to setup address manipulaton in Flexbus core... Is there a way to resolve this issue?

Best,

Primoz

[soledad]

Hello Primoz Rebec,

Please check the below application note (pages 17,18) and let me know if this helps.

http://cache.freescale.com/files/microcontrollers/doc/app_note/AN4393.pdf

Have a great day,
Sol

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------