External SDRAM and clock transition

[pradeeshmt]

Hi,

I am working in K81 platform. My application requires more memory so i integrated external QSPI flash and external SDRAM everything is working fine with 120MHz normal run mode. But i need more speed, and i changed clock in to HSRUN (150MHz), i know flash write/erase will not work in HSRUN (i need flash write/erase in my app). So i wrote a code for clock transition when i enter flash operation. This transition is working without SDRAM but with SDRAM initialisation this transition code hangs in SIM_CLKDIV1 register writing. That means,

1. I started with HSRUN - fine
2. I initialized SDRAM - fine
3. Try to change clock - problem!!! 

If i comment 2nd step, no issue..

So, in this case what step i need to do? Because i need high speed execution of code, external flash, external RAM and internal flash erase/write in my application.

[jorge_a_vazquez]

Hi pradeesh thomas 

When you initialize the SDRAM, you need to specify the clock source speed to calculate the auto refresh timing, as long as the clock source of the SDRAM is from the bus clock, then if you need to change to HSRUN, you need to write to SIM_CLK register.

If you need to change the clock speed of your clock source, then you will need to first deinitialize the SDRAM module and then after you make the change of the clocks, reinitialize the module.

Hope this helps

Best regards

[pradeeshmt]

thank you for your reply Jorge,

I tried to deinitialise SDRAM but its not worked. please look into my code. SDRAM controller de-initialization ok. Is there any SDRAM_deinitSequence like "SDRAM_InitSequence" .

status_t SDRAM_Init(SDRAM_Type *base, uint32_t busClock_Hz)
{
sdramc_config_t config;
sdramc_refresh_config_t refConfig;
sdramc_blockctl_config_t ctlConfig;

/* SDRAM initialization. */
CLOCK_SetClkOutClock(0);//0
SIM->SOPT2 = (SIM->SOPT2 & ~SIM_SOPT2_FBSL_MASK) | SIM_SOPT2_FBSL(3);
CLOCK_EnableClock(kCLOCK_Flexbus0);
FB->CSPMCR = FB->CSPMCR & ~FB_CSPMCR_GROUP2_MASK | FB_CSPMCR_GROUP2(2);
FB->CSPMCR = FB->CSPMCR & ~FB_CSPMCR_GROUP3_MASK | FB_CSPMCR_GROUP3(2);
FB->CSPMCR = FB->CSPMCR & ~FB_CSPMCR_GROUP4_MASK | FB_CSPMCR_GROUP4(2);
FB->CSPMCR = FB->CSPMCR & ~FB_CSPMCR_GROUP5_MASK | FB_CSPMCR_GROUP5(2);

/* SDRAM refresh timing configuration. */
refConfig.refreshTime = kSDRAMC_RefreshThreeClocks;
/* Refresh time 4096 rows/ 64ms. */
refConfig.sdramRefreshRow = 15625;
refConfig.busClock_Hz = busClock_Hz;

/* SDRAM controller configuration. */
/* Port size: 16 bit, Command bit location: bit 19. */
ctlConfig.portSize = kSDRAMC_PortSize16Bit;
ctlConfig.location = kSDRAMC_Commandbit19;
ctlConfig.block = kSDRAMC_Block0;
/* SDRAM with trcd-15ns(min), trp-15ns(min), tras-37ns (min). */
ctlConfig.latency = kSDRAMC_LatencyOne;
ctlConfig.address = SDRAM_START_ADDRESS;
ctlConfig.addressMask = 0x7c0000;
// ctlConfig.addressMask = 0xf80000;

config.refreshConfig = &refConfig;
config.blockConfig = &ctlConfig;
config.numBlockConfig = 1;
/* SDRAM controller initialization. */
SDRAMC_Init(base, &config);

/* SDRAM initialization sequence. */
return SDRAM_InitSequence(base, kSDRAMC_Block0, kSDRAM_MrsBurstLenOne, kSDRAM_MrsSequential, kSDRAM_MrsLatencyTwo,
kSDRAM_MrsStandOperation, kSDRAM_MrsWriteBurst);
}
status_t SDRAM_Deinit(SDRAM_Type *base)
{
SDRAMC_Deinit(base);
FB->CSPMCR = 0x00000000;
CLOCK_DisableClock(kCLOCK_Flexbus0);
SIM->SOPT2 = (SIM->SOPT2 & ~SIM_SOPT2_FBSL_MASK);
return 0;
}

[pradeeshmt · Accepted solution]

I got it!

Added kSDRAMC_AutoRefreshDisableCommand in the deinitilization code.

After this i could change the clock. But if you enabled the system cache, you will face issue in SDRAM init/deinit function. So before deinit/init external SDRAM you have to disable system cache.

LMEM_EnableSystemCache(LMEM, false);