Easiest way to expose the System Clock to an external pin?

[pmt]

As I am slowly earning my PhD in the Freescale peripheral set configuration, can someone point me to the easiest way to bring the system (core) clock to an external pin for verification on a scope?  I believe the system clock setup is wrong and running fast on my tool chain.  As evidence my UART5 is running ~8.5% fast.   I am using the TWR-K60F120M development board.

Thanks,

pmt

[admin]

You can configure FB_CLKOUT on PTC3 to view the clock.

[pmt · Accepted solution]

SOLUTION:

I had some trouble getting FB_CLKOUT going, but I managed to get TRACE_CLKOUT out to pin with some example code found in the forums.  NOTE: The TRACE_CLKOUT will be half the CPU clock.  This is easily available on the K60_120 board.

// Pin mux configured as ALT5
PORTC->PCR[3] = (5L << 8);

// Set the trace clock to the core clock frequency
// TRACE_CLKOUT is half of CPU clock
SIM->SOPT2 |= SIM_SOPT2_TRACECLKSEL_MASK;
// Enable the TRACE_CLKOUT pin function on PTA6 (alt7 function)
PORTA->PCR[6] = ( PORT_PCR_MUX(0x7));

[albertolubeiro]

Hi,

I´m having troubles getting de clock signal out by PTC3 pin.

I have configured PTC3 to FB_CLKOUT with Pin mux configured as ALT5 but no results

any idea?

Thanks

[santiago_gonzal]

Hello Alberto,

You can create a new baremetal project and configure with processor expert the CLKOUT pin control.  To change the configuration, go to the Cpu component inspector (Remember to select "expert" on the right upper corner to see all the options)

In the Cpu component inspector go to: Internal Peripherals->System Integration Module->CLKOUT pin control.

I attached one project as an example.AS you don't specify which MCU you are using, I have used K60. I've chosen PTC3 as pin and MCGIRCLK as the signal.

I hope this helps you!

[albertolubeiro]

Hola Santiago,

Te contesto en español porque supongo que serás español con ese nombre y apellido jejeje.

Muchas gracias por tu respuesta tan rápida. Me ha sido de gran ayuda. En el fichero Cpu.c está el código que necestiaba, la inicialización del PTC3. Lo he añadido y funciona perfectamente.

Por cierto yo tb uso el K60

Muchas gracias de nuevo.

Saludos

[albertolubeiro]

Hi,

I have a problem with a Kinetis K60.

I have got the clock out by the PTC3 pin. The problem is that the signal of PTC3 is 90 degrees out of phase relative to the oscilator signal and also is of smaller amplitud. (6Vpp oscilator, 3Vpp at the PTC3).

Any idea of what is happening. May be i have to configure any register or something.

Thanks

[santiago_gonzal]

Hello Alberto,

The GPIO is 3V, so its normal for the Vpp value to be between 0 and 3V.

Regarding the phase, you have a multiclock generator between your oscillator and the MCGOUT signal (Which is the one you are reading in the PTC3). So it's also normal for the two signals to be out of phase, because they are not the same signal.

Regards,

Santiago

[albertolubeiro]

Hello Santiago,

First of all, thanks for your quick response.

OK, both issues are anormal but the ethernet comunication fails when the phy is sourced by PTC3 and is always fine when is sourced by the oscilator signal. I don´t understand.

I hope i explain well. Sorry for my english.

Best regards.

[santiago_gonzal]

Hello Alberto,

Please check ENET_MSCR register in the RM of K60:

MII Speed Control Register (ENET_MSCR)

MSCR provides control of the MII clock (MDC pin) frequency and allows a preamble

drop on the MII management frame.

The MII_SPEED field must be programmed with a value to provide an MDC frequency

of less than or equal to 2.5 MHz to be compliant with the IEEE 802.3 MII specification.

The MII_SPEED must be set to a non-zero value to source a read or write management

frame. After the management frame is complete, the MSCR register may optionally be

cleared to turn off MDC. The MDC signal generated has a 50% duty cycle except when

MII_SPEED changes during operation. This change takes effect following a rising or

falling edge of MDC.

If the internal module clock is 25 MHz, programming this register to 0x0000_0004

results in an MDC as stated in the following equation:

25 MHz / ((4 + 1) x 2) = 2.5 MHz

I hope this helps.

[albertolubeiro]

Hi Santiago,

What i didn´t metioned before is that i´m using the FNET sources.

I am using DP83848C

The comunication with PHY via MDIO and MDC signals is OK. The problem appears  when i try to conect with a terminal like Hercules. It fails when the PIN 34 of phy is sourced by PTC3 and is always fine when is sourced by the oscilator signal.

Thanks!

[LuisCasado]

Hi Alberto,

We recommend to use the PHY output clock to drive the Kinetis clock. In that way, MAC and PHY are using the same clock (phase and ppm variation). The difference in phase and stability of the clock coming from FLL/PLL can affect the MAC-PHY interface, specially at 100Mbps. Probably would work fine @10Mbps. In our TWR system, we use that approach, K60 is clocked out of PHY clock output.

Best Regards,

Luis

[albertolubeiro]

Hi Luis,

Ok, then we´ll change that.

Thanks and best regards.

Alberto

[Sören]

Use the PIT!

on every interrupt toggle an Output... take a scope... and you should see ~8.5% abberation.

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