Does the KL26 digital outputs continue to drive output pins in all the various Stop sleep modes?

[nurichard]

Hello,

The rev 3.2 October 2013 KL26 Sub-Family Reference Manual KL26P121M48SF4RM states in table 7-2 (pg 161) that the GPIO module goes into the following conditions in the various stop sleep modes:

Stop: static output, wakeup input / Fully functional in PSTOP2

VLPS: static output, wakeup input

LLS: static, pins latched

VLLS: OFF, pins latched

Q1) Is this telling me that the GPIO module registers will retain their values except in VLLS (where it is OFF)?

As there is no entry in this table for the PORT control (described in chapter 11), does this mean that it continues to operate the same as it does in run mode, even in all VLLS modes?

My particular interests are in confirming that:

Q2) the outputs continue to be driven with the same strength as in run mode?

Q3) input pull-ups / pull-downs continue to operate as in run mode?

Q4) will the PORT registers retain their values in all modes?

Q5) does an output pin continue to be low or high when changing between any mode?

Thank you all for your help,

Richard

[Paul_Tian · Accepted solution]

Hi, Nurichard

From chapter "Power Management" In our reference manual, you can find OFF = Modules are powered off; module is in reset state upon wakeup. So back to your questions.

A1: Yes, you are correct. No, you cannot operate register in static and OFF status.

A2: Yes, you are correct.

A3: Yes, pull-up and pull-down still on.

A4: Yes, GPIO will latch their status.

A5: Yes, correct.

Hope my reply can help you.

Best Regards

Paul

[nurichard]

My thanks for you help,

Richard

[nurichard]

For those who may find this, here are some observations:

* The pins configured as GPIO push-pull outputs do continue to drive low / high in VLSS0 (I didn't measure the actual drive strength)