Disable all digital filters..

[pietrodicastri]

Good morning..

I wander what's wrong here ???

I want to disable all filters...

for ( int i = 0; i < HW_GPIO_INSTANCE_COUNT; i++  )

{    

     HW_PORT_DFER_WR( g_portBaseAddr[ i ],  0 );

}

Thank You

	}

[pietrodicastri]

Yes...

Not before.. That's it

[pietrodicastri]

Hi Yasuhiko

I tried but I always have a protection fault in the Default_Handler() trap.

I can set the length of the filter but not reset the filter. I am not depending on the functionality so

I will go on anyway,

If You have occasion to test on the K64 replay when You want,

Thank you for the support.

Pietro

[Hui_Ma · Accepted solution]

Hi Pietro,

When you want to access the Port Control registers (PORTx_), it need at first to enable related PORT clock gate at System Clock Gating Control Register 5 (SIM_SCGC5) [PORTx] bit.

Wish it helps.

Have a great day,
best regards,

Ma Hui

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[pietrodicastri]

Hello Yasuhiko

I am now reading the header file of the sdk : fsl_port_hal.h.

A comment states:

/*!

* @brief Configures the maximum size of the glitches (in clock cycles) that the digital filter absorbs

*        for enabled digital filters. Glitches that are longer than this register setting

*        (in clock cycles)  pass through the digital filter, while glitches that are equal

*        to or less than this register setting (in clock cycles)  are filtered. Changing the

*        filter length should only be done after disabling all enabled filters.

*

* @param baseAddr  port base address

* @param width  configure digital filter width (should be less than 5 bits).

*/

static inline void PORT_HAL_SetDigitalFilterWidth(uint32_t baseAddr, uint8_t width)

So it seems the suggestion is to disable the filter then to change the length. Can You give me the page of the reference manual

where it explained differently?

Thank You for the assistance...

Pietrp

[yasuhikokoumoto]

Hi Pietro,

there are no different parts from the document but the header comments describe behavior when the digital filter is enabled.
If it is disabled we can refer to the DFER explanations as the following (p.287 of K64 TRM).

The output of each digital filter is reset to zero at system reset and whenever the digital filter is disabled.

By this statements, I think the digital filter would always output "0" when if was disabled. If my understanding was incorrect, please let me know.

Best regards,
Yasuhiko Koumoto.

[pietrodicastri]

Good morning

I Am using the K64 on the FRDM board. The DFER is present.

Suggetsions??

Thank You

[yasuhikokoumoto]

Hi Pietro,

I think your intention is to bypass the digital filter. However, it seems to be impossible according to the Technical Reference Manual. If DFER set to "0", the digital filter output would be "0". I think you could only make DFER ON and the filter length make "1" by PORTx_DFWR. I guess if DFWR was "0", then the digital filter would be bypassed. As I don't have K64 board, I cannot make experiments.

Best regards,
Yasuhiko Koumoto.

[yasuhikokoumoto]

Hi Pietro,

what is your device or part? Does your device have DFER?

Best regards,

Yasuhiko Koumoto.