Dear NXP engineers:
I'm debugging the kea8 FTM moudule. The system CLK is 40Mhz, and according to the reference sheet that the FTM counter clk source from system clock.Is that means that the FTM counter clk also up to 40Mhz?
But according to caculate period of pwm out ,it seems like couter clk just up 20Mhz (the FTM PS ,prescale factor selection is 000,divide by 1).The setting as below.
ICS->C1|=ICS_C1_IRCLKEN_MASK; /* Enable the internal reference clock*/
ICS->C1 |= ICS_C1_CLKS(0);
ICS->C1 |= ICS_C1_IREFS_MASK;
ICS->C3= 0x90; /* Reference clock frequency = 31.25 KHz*/
while(!(ICS->S & ICS_S_LOCK_MASK)); /* Wait for PLL lock, now running at 40 MHz (1280 * 31.25Khz) */
ICS->C2|=ICS_C2_BDIV(0) ; /*BDIV=1.
SIM->CLKDIV |= SIM_CLKDIV_OUTDIV1(0);
SIM->CLKDIV &= ~SIM_CLKDIV_OUTDIV3_MASK;
SIM->CLKDIV |= SIM_CLKDIV_OUTDIV2_MASK; /*Bus clock = 20 MHz*/
So my question is if this FTM counter clk can up to 40Mhz like as system clk .?
Hi 展辉 刘,
As it is mentioned in the reference manual in chapter 26.4.1 the FTM has only the system clock domain (48MHz).
If you are using FTM in PWM mode I'd recommend you to check whether you are using Center-Aligned PWM or Edge-Alined mode as the formulas to calculate the period are different (chapter 26.4.6 and 26.4.7), I think that's where you are getting half of the expected frequency from.