Can Kinetis K and KL parts that have unallocated non-core NVIC entries be used for SW service requests?

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Can Kinetis K and KL parts that have unallocated non-core NVIC entries be used for SW service requests?

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nurichard
Contributor III

Hello,

I am looking at the NVIC table for a KL16 part http://cache.freescale.com/files/microcontrollers/doc/ref_manual/KL16P80M48SF4RM.pdf which lists 3 Non-Core vectors as having no source module (IRQ 4, 24 and 29).

It would be highly desirable for me to be able to have code running in a non-interrupt context to be able to set these vectors as pending to be able to trigger an interrupt vector hanging off them as a way to temporarily switch execution into an interrupt context.

This is similar to what you might do with a Supervisor / System call mechanism if you had an OS (except my use case is not as complex)

Can anyone tell me if the ARM core of all Kinetis parts has the entire vector table implemented and active (according to the list in it's reference manual to be used as above) or do some parts not have any implementation for those vectors?

Whilst I can obviously check this for a specific revision for a particular part I happen to have; I want to know what happens across the range so I can decide if the above should be considered or if only the Supervisor vector (ARM core vector #11) is safe to use (requiring a more typical OS like implentation)

Thank you for your help,

Richard

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nurichard
Contributor III

For the assistance of others looking at this thread;a service support thread was started to try and answer this question.  A relevant response that expands upon Hui_Ma's response was given to me:

"""

Software Triggered Interrupt Register, STIR, which Provides a mechanism for software to generate an interrupt.

Writing to the STIR, software can use an exception number to set the corresponding pending register (ISPR) bit to 1. Only external interrupts can be made pending using this method. The processor ignores any attempt to write an exception number:

* in the range 0-15

* that corresponds to an interrupt that it does not support.

Then I checked if KL and K parts support STIR register.

KL parts doesn't support STIR register and K parts support STIR register.

That means customer can use software trigger interrupt with K parts.

"""

Understandably the support staff does not have access to the H/W chip design so is answering based on some non-specific documentation (and therefore cannot check all the revisions of all the parts); I clearly had unreasonable expectations in my original question

Some points of interest for readers:

* The ARM IP M0+ core does have an ISPR register (see ARM Information Center) to set non-core interrupts as pending where ARM Information Center states "The number of functional interrupts is configured by the MCU implementer" which suggets that Freescale can chose to not support some given non-core vectors and therefore prevent the associated handlers from running if an attempt to set it as pending was made using the ISPR register.

* A KL26 Freescale processor that I happen to have lying around allows you to use the ISPR register to trigger a non-core interrupt and have execution change to it's interrupt handler both with an external H/W trigger source (such as CMP0) and an interrupt that is not listed as having a hardware trigger (such as IRQN 4 which is listed as not having a Hardware source in it's reference manual).  This was determined by entering a handler address into an appropriate NVIC table location when compiling with GCC, setting a breakpoint using GDB inside the handler and watching the handler get executed when the interrupt is enabled and then set pending by the software.

I have been unable to confirm that all the 32 non-core NVIC entries supported by a M0+ core have been configured to be usable by Freescale for the use described above in all it's KL parts.

I have not been able to determine how many of the M4 core 256 possible non-core NVIC entries have been configured to be usable by Freescale for the use described above in all it's K parts.

I therefore do not known that if I utilise the behaviour that I tested above on a specific revision of a specific KL26 part that the code will function on a different silicon revision or different part by looking at the documentation (and adjusting the IRQN's used to avoid clashes obviously); I consider this to be a failure of the documentation.

I hope this has helped any others who are interested / trying to do a similar thing,

Richard

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angelgenchev
Contributor I

Thanks for this information. I just have asked myself the same question.

Actually, for the same purpose, I use a well documented and available software triggered IRQ - entry 14 in vector table (PendableSrvReq) (PendSV_Handler in my startup.s), but it would be nice to use the other "reserved" entries also to avoid the need of checking which one of the (lower priority) tasks should be executed between the different software modules.

By coincidence, I also work on a KL26 CPU. The SVCall Handler is not an option, because it can't bre deferred, e.t. it happens immediately or if it has not enough priority, it fails in the HardFault handler (by ARM documentation, not personally tested).

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Hui_Ma
NXP TechSupport
NXP TechSupport

Hi Richard,

I check both ARM Cortex M4 and M0+ with SVCall exception, customer can call SVC instruction to generate an interrupt.

The reserved IRQ 4,24and 29 for KL16 could not be trigger,there need hardware module to trigger the interrupt source.


Wish it helps.
best regards
Ma Hui

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