Can I trap a watchdog in the MKL17?

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Can I trap a watchdog in the MKL17?

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nnewell
Contributor II

The MKL17 has a builtin watchdog but there doesn't appear to be any way to trap the watchdog event itself. The processor simply resets and I can read the RCM_SRS0[WDOG] bit to be set so on that next reset I can determine a watchdog occurred, but I'd like to generate a traceback and burn it into flash before resetting the unit. Is there anyway to configure the unit to do this or do I need an external watchdog?

Thanks.

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mjbcswitzerland
Specialist V

Nick

The COP watchdog in the KL17 doesn't support an interrupt. There is interrupt capability in some other parts which use different watchdog modules but these give the handler about 128 clocks to perform their work and so programming to Flash doesn't work since it takes too long - the idea is to save some registers to SRAM instead.

However there is an easy workaround:
1. Use the watchdog as you have it to cause a reset after the defined time without triggering.
2. Add a HW timer with a slightly shorted timeout that you re-trigger at the same time as you re-trigger the COP watchdog. This has an interrupt enabled with highest priority.

3. When this SW timer times out it is signalling a problem since the watchdog will imminently timeout too and cause a reset so you can use it to do the same that that you wanted to do in the missing HW watchdog interrupt (although you have more time and so could even save information to Flash).

Some may say that this is not fully reliable since if interrupts are disabled when the watchdog is about to fire the handler will not be caused - however this is equally true for the watchdog's own interrupt - it will also be blocked if interrupts are globally disabled or it has a lower priority than an interrupt that is causing a failure.

Furthermore, a frequent cause of watchdog timeouts is a hard-fault which should also be used to collect information.

Regards

Mark

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750 Views
mjbcswitzerland
Specialist V

Nick

The COP watchdog in the KL17 doesn't support an interrupt. There is interrupt capability in some other parts which use different watchdog modules but these give the handler about 128 clocks to perform their work and so programming to Flash doesn't work since it takes too long - the idea is to save some registers to SRAM instead.

However there is an easy workaround:
1. Use the watchdog as you have it to cause a reset after the defined time without triggering.
2. Add a HW timer with a slightly shorted timeout that you re-trigger at the same time as you re-trigger the COP watchdog. This has an interrupt enabled with highest priority.

3. When this SW timer times out it is signalling a problem since the watchdog will imminently timeout too and cause a reset so you can use it to do the same that that you wanted to do in the missing HW watchdog interrupt (although you have more time and so could even save information to Flash).

Some may say that this is not fully reliable since if interrupts are disabled when the watchdog is about to fire the handler will not be caused - however this is equally true for the watchdog's own interrupt - it will also be blocked if interrupts are globally disabled or it has a lower priority than an interrupt that is causing a failure.

Furthermore, a frequent cause of watchdog timeouts is a hard-fault which should also be used to collect information.

Regards

Mark

749 Views
nnewell
Contributor II

Hi Mark, I'm a bit low on timers but I'll give this a try. Thanks for the quick response.

Nick

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