Bandgap reading accuracy (bandgap is enabled in PMC)

[ryanparasram]

Hi,

I am using a S9KEAZN64AMLC controller with a 5.3V power supply. I have a scope on the power supply and see that it is stable.

I have the PIT triggering ADC conversions at 500us.

The ADC is configured to take 4 12 bit readings with 16 bit right justified results.

The ADC is configured as

- Discontinuous mode OFF, Low power mode OFF, ADC clock 1Mhz, Conversion time 40us, Sample time 23.5 clock periods.

- When I read the bandgap and dump the results to a serial port, I see the 8 LSB's changing, corresponding to about 1.11 to 1.21V

- The CPU is clocked at 8Mhz (both Core and Bus)

I was hoping that the values will have good precision and maintain at least 4LSB's.

Could you tell me what I am doing wrongly and what I may try?

Thanks,

Ryan

[jeremyzhou]

Hi Ryan,

I was wondering if you can share your demo, then I could run this demo with the TRK-KEA64 board and reproduce this issue.

I'm looking forward to your reply.
Have a great day,
Ping

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[ryanparasram]

Ping,

I have the driver code generated from Processor Expert and built in Keil uVision 5.12. The code generation simply has the settings stated previously.

I have the code compiling with a proprietary telemetry application. Before working to separate the telemetry app from the bandgap and serial routines, could you let me know what configuration will work for the bandgap?

I can easily modify my code from PE to try different configurations.

Following another suggestion, I slowed the ADC clock down to close to the minimum (0.4Mhz), with the following config

12 bit

Sample time 3.5 clock periods

Conversion time 48.48us

ADC clock 412.5khz

Conversion time 56.382us

And I still get the following results

(Note that the PIT triggers a reading every 500us and I get 8 buffered readings)

Try 1: BG0368  BG03A3  BG039E  BG0397  BG0368  BG035B  BG039D  BG0374 BG0382

Try 2: BG03A2  BG03B7  BG037B  BG036B  BG0382  BG0377  BG03A6  BG039A BG038F

Try 3: BG03AC  BG03AB  BG037F  BG039D  BG039C  BG0385  BG0365  BG03AE BG0394

Regards,

Ryan

P.S. - I will get a Dev board and see if I get different results. Could you configure your dev board in the meanwhile and let me know if you see a 12 bit stable reading?

Note that I am using PE 10.4.0 with controller SKEAZN64MLC2 selected.

It is configured to use the internal oscillator 31.25khz with the trim values loaded.

FEI mode is used for an FLL output of 32Mhz and an ICS output clock of 8 MHz. The Core and Bus clocks are set to 8Mhz.

[ryanparasram · Accepted solution]

I took my previous settings

Sample time 3.5 clock periods

Conversion time 48.48us

ADC clock 412.5khz

Conversion time 56.382us

And slowed down the Sample Time to 23.5 clock periods.

I then took 800 readings several times and observed a mean of 1.16 with std dev 0.01 (using my actual measured rail voltage of 5.2V).

I then calculated the number of readings over which I needed to take the mean.

Thanks to all for the replies.

[jeremyzhou]

Hi Ryan,

I had encountered the similar issue when I used the PE component to generate the code for sampling the Bandgap value, and the Bandgap vaules were also variable just like you got.

The issue bothered me a lot. Finaly, I figured out this issue, the PE default don't enable the Bandgap buffer.

So I'd like to suggest that you'd better to check out the code that the PE 10.4.0 generated.
Have a great day,
Ping

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[ryanparasram]

Ping,

As stated in the heading of the post, the bandgap buffer is enabled.

===========================================================

My main() calls PE_low_level_init() and has the following code

  /* PMC_SPMSC1: LVWACK=1,LVWIE=0,LVDRE=1,LVDSE=0,LVDE=1,??=0,BGBE=1 */

  PMC_SPMSC1 = (uint8_t)((PMC_SPMSC1 & (uint8_t)~(uint8_t)(

                PMC_SPMSC1_LVWIE_MASK |

                PMC_SPMSC1_LVDSE_MASK |

                0x02U

              )) | (uint8_t)(

                PMC_SPMSC1_LVWACK_MASK |

                PMC_SPMSC1_LVDRE_MASK |

                PMC_SPMSC1_LVDE_MASK |

                PMC_SPMSC1_BGBE_MASK

              ));

===========================================================

From my previous readings, you can see that they are not random.

For the rail voltage of 5.3V, the counts of 0x0365-0x03B7 correspond to a bandgap voltage of 1.12-1.23V.

Note that temperature is constant.

I have added 1uF to the voltage rail and will repeat the measurements. If this is the expected precision at constant temperature I need to select an alternative.

Is there a paid option for support?

Regards,

Ryan

[jeremyzhou]

Hi Ryan,

Sorry, I missed this important information in your first thread.

To be honest, I can't give the exactly answer about the vaule between the 0x0365~0x03B7 whether meet the precision of the bandgap in the S9KEAZN64AMLC now.

I think I need to contact with the AE team about this issue.

I'll inform you ASAP after I receive the reply from the AE team.
Have a great day,

Ping

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[ryanparasram]

The datasheet claims that the BG should be 1.14 to 1.18 for 5VDC at 125DegC. My parameters are 5.22VDC at 70DegF (21DegC).

That corresponds to 5 stable bits. I am seeing only 4 stable bits.

I also hoped that the spec range expressed a drift with temperature and not instability at 1 temperature. I have seen >8 bit stability on TIMSP430 and PIC16 parts.

Note that I added an extra 1uF (it was previously .1uF) across the rails and reference (pins 3,4 and 5,6) and the bandgap had the same performance. The other ADC readings had

only 3 LSB's changing which shows that the ADC configuration is valid.

I will use an alternative reference as suggested by Earl. The REF50xx series looks good or I may characterize my 5V rail over temperature and just use that. It seems to be 5.3V +- 2%.

I really appreciate the replies.

[Hui_Ma]

Hi Ryan,

Today, I do a test with TRK-KEA64 board with bandgap measurement.

My test result the ADC_R register value is  within [0x3bb ~ 0x3bf] range.

Below is my ADC initialization code, which I use slow ADCK clock and use long sample time:

#define TWELVE_BIT     2

ADC_Init(23,TWELVE_BIT);    /* Configure ADC channel 3 in 8-bit resolution mode */

/***********************************************************************************************

*

* @brief    ADC_Init - Initiates the Channeln to read the value of the ADC channel

*             

* @param    Channel to init and resolution

* @return   none

*

************************************************************************************************/ 

void ADC_Init(UINT8 channel, UINT8 mode)

{

    SIM_SCGC |= SIM_SCGC_ADC_MASK;                /* Enable bus clock in ADC*/

    ADC_SC3 |= ADC_SC3_ADICLK(0b00);            /* Bus clock selected*/

    ADC_SC2 |= 0x00;                            /* Software Conversion trigger, disable compare function*/

    ADC_SC2 |=ADC_SC2_REFSEL(0b01);            /* Select VDD and VSS as voltage reference source*/

    ADC_SC1 = 0    ;                                /* Enable ADC by setting ADCH bits as low*/

    ADC_SC1|= ADC_SC1_ADCO_MASK;                  /* Continuous mode operation */   

    ADC_APCTL1 |= ADC_APCTL1_ADPC(1<<channel);  /* Channel selection */   

    ADC_SC3 |= ADC_SC3_MODE(mode);                /* 8,10,12 bit mode operation */

    ADC_SC3 |= ADC_SC3_ADLSMP_MASK | ADC_SC3_ADICLK(1) |ADC_SC3_ADIV(3);

}

The ADC module is using VDDA and VSSA as reference voltage. I measure the TRK-KEA63 VDDA voltage is about 4.88V.

Then, the measured Bandgap voltage is about 1.143V.

Wish it helps.
best regards
Ma Hui

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[egoodii]

We're still mixing stability and accuracy here -- but the bottom line on accuracy is that said 1.14-1.18V range is still 1.16V+/-1.72%, at that ONE test value.  If you want any kind of real accuracy, the external REF30xx or 50xx is the way to go!  I look forward to some results!

[egoodii]

One quick comment --- while the title talks about Accuracy, the content is all about reading-stability.  When it comes to accuracy, the on-chip reference is 'poor' at best.  For 70cents (REF3030, 0.2% 75ppm) to a buck-and-a-half (REF5030, 0.1% 8ppm), you will do MUCH better feeding VrefH from an external reference regulator.

[Hui_Ma]

Hi Ryan,

First of all, it need to keep the ADC VERFH and VREFL be stable.

We recommend customer to use VREFH = VDDA and VREFL =VSSA, while customer also could select any stable voltage to VREFH and VREFL.

Then customer can select the ADC with long sample time in software.

Wish it helps.
best regards
Ma Hui

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[ryanparasram]

Hi Ma,

I use Processor expert to configure the device and I see that VDDa/REFH and VSSA/VREFL are selected as the references.

I scope the VDD/VSS lines and the voltage is stable. The readings below imply a change in the 5V rail of 0.3V for the short sample and 0.17V for the long sample (assuming a 1.16 BandGap).

I tried both long (23.5 clock periods) and short (3.5 clock periods) sample times with the same result. PE prevents selecting invalid options.

The full ADC config is now

Short sample time (3.5)

Conversion time 20us

ADC clock 1Mhz

I get 8 results as follows (note variation in bit 7)

BG0371  BG038A  BG03A5  BG0362  BG0389  BG039A  BG0386  BG039A

Long sample time (23.5)

Conversion time

ADC clock 2Mhz

I get 8 results as follows (note variation in bit 7)

BG0396  BG038A  BG0397  BG038B  BG0397  BG0397  BG037A  BG0395

Do you have a sample Keil project that I may use to read the bandgap a few times?

Could there be a bug in PE 10.4.0?

I really appreciate the quick response.

Thanks and regards,

Ryan