Are there any requirements on tolerance the frequency of EXTAL1/XTAL1 clock?

[tanaka_shinsuke]

Dear Sirs or Madams,

Please let me have following two questions regarding tolerance the frequency of EXTAL1/XTAL1 clock on MK61FX512VMJ15;

Q1.

Are there any requirements on tolerance the frequency of EXTAL1/XTAL1 clock?

Q2.

On our PCB, 12MHz crystal oscillator is connected to MK61FX512VMJ15 EXTAL1/XTAL1.

And according to the circuit analysis results done by the vendor of the crystal oscillator,

the frequency deviation is -22pm on our current circuit.

Will 12MHz with -22ppm deviation cause any problems on MK61FX512VMJ15?

Best regards,

Shinsuke Tanaka

[miduo]

Hello,

Well actually, we don't have any crystal accuracy required.That means we do not provide any tolerance spec or restriction regarding the PPM, this characteristic will depend entirely on customer final application.
If your application for example, requires a high precision clock then you will need a low PPM.

[tanaka_shinsuke]

Dear Fang Li,

I'm too sorry for my delayed response, and I appreciate your response.

>That means we do not provide any tolerance spec or restriction regarding the PPM,

>this characteristic will depend entirely on customer final application.

Could you please let me know additional questions regarding your above comment?

Q.

I now understand as follows;

  The clock signal generated by the crystal oscillator

  which is connected to MK61FX512VMJ15 EXTAL1/XTAL1 pins

  is also used as internal clocks of MK61FX512VMJ15.

If my above understanding is correct, I guess that too big PPM on the clock on EXTAL1/XTAL1 pins

will cause malfunctions of MK61FX512VMJ15.

Actually, according to our previous discussions shown on 

Please let me know when Lockup event occurs ,

there is the below comment;

"the LockUp event may occur when Circuit Matching between MK61FX512VMJ15 and external crystal oscillator

is NOT adjusted appropriately". 

It seems for me that this comment also indicates that 

too big PPM of the frequency tolerance will cause malfunctions of MK61FX512VMJ15,

because I understand that lack of Circuit Matching causes too big PPM of the frequency tolerance.

So, from my understandings and guess shown above,

I'm wondering why any tolerance spec or restriction regarding the PPM are NOT provided.

Could you please let me know the reason?

Or, if there are any mistakes on my understandings or guesses shown above,

please let me know it.

I'm sorry for my ambiguous question, but I need your help to deepen my understandings

regarding this topic.

Best regards,

Shinsuke Tanaka

[miduo · Accepted solution]

Hello,

Sorry for the late response. I understood your feeling. However the reality is we really do not provide tolerance spec you mentioned. The reason I may also mentioned already. I will check internally if any more comments I can get.

[tanaka_shinsuke]

Dear Fang Li,

>However the reality is we really do not provide tolerance spec you mentioned.

I now understand as follows;

   -If the PPM of the frequency tolerance is "excessively high", it is possible that LockUp event occurs.

  -On the other hand, regarding how much PPM is "excessively high", 

   no specifications or restrictions are shown by NXP.

   But anyway as long as the PPM is within the value in common-sense, here I mean 100ppm or smaller,

   K61 works normally.

>I will check internally if any more comments I can get.

I close this Q&A per your previous comments.

But if there is any additional information, please share it with me.

I appreciate your  cooperation.

Best regards,

Shinsuke Tanaka